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order number: 315039-003US december 2007 intel ? 81341 and intel ? 81342 i/o processors datasheet product features intel? 81341 i/o processor contains one integrated intel xscale ? processor intel? 81342 i/o processor contains two integrated intel xscale ? processors processor features 800 mhz and 1.2 ghz arm* v5te compliant instruction/data cache: 32 kbyte, 4-way set associative, nru replacement algorithm, lockable unified level 2 cache: 512 kbyte set associative, nru replacement algorithm 128-entry branch target buffer 8-entry write buffer 8-entry fill and pend buffer internal bus 400 mhz/128-bit can support either pci-x or pci express* as an endpoint support for pci express* lane widths of x1, x2, x4, x8 multi-ported memory controller intel xscale? processor inputs and north internal bus, south internal bus and adma input ports pc3200 and pc4300 double data rate (ddr2 400, ddr2 533) up to 4 gb of 64-bit ddr2 400, ddr2 533 optional single-bit error correction, multi- bit detection ecc support supports registered and unbuffered ddr2 memory 36-bit addressable 32-bit memory support integrated sram memory controller (1 mb) address translation unit 2 kb or 4 kb outbound read queue 4 kb outbound write queue 4 kb inbound read and write queue two programmable 32-bit timers and watchdog timer sixteen general purpose i/o pins three i 2 c bus interface units two uart (16550) units 64 byte receive and transmit fifos 4 pin master/slave capable peripheral bus interface 8-, 16-bit data bus with two chip selects 25 demultiplexed address lines interrupt controller unit four priority levels interrupt pending register vector generation 16 external interrupt pins with high priority interrupt (hpi#) 1357-ball, flip chip ball grid array (fcbga), 37.5 mm x 37.5 mm and 1.0 mm ball pitch application dma controller three independent channels connected to the mcu and the south internal bus 4 kbyte data transfer queue crc 32c calculation performs optional xor on read data
intel ? 81341 and 81342 i/o processors datasheet december 2007 2 order number: 315039-003US leg al li nes and dis clai mers information in this document is provided in connection with intel? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intels terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear fac ility appli cations. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the a bsence or characteristics of any features or instructions marked reserved or undefined. intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the information here is subject to change without notice. d o not finalize a design with this information. the products described in this document may contain design defects or errors known as errata which may cause the product to dev iate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an order number and are referenced in this document, or other intel literature, may be obtained by calling 1-800-548- 4725, or by visiting intels web site . intel processor numbers are not a measure of performance. processor numbers differentiate features within each processor family , not across different processor families. see http://www.intel.com/products/processor_number for details. code names are only for use by intel to identify products, platforms, programs, services, etc. (products) in development by i ntel that have not been made commercially available to the public, i.e., announced, launched or shipped. they are never to be used as commercial name s for products. also, they are not intended to function as trademarks. bunnypeople, celeron, celeron inside, centrino, centrino logo, core inside, flash file, i 960, instantip, intel, intel logo, intel386, intel486, intel740, inteldx2, inteldx4, intelsx2, intel core, intel inside, intel inside logo, intel. leap ahead., intel. leap ahead. logo, intel n etburst, intel netmerge, intel netstructure, intel singledriver, intel speedstep, intel strataflash, intel viiv, intel vpro, intel xscale, itanium, itanium in side, mcs, mmx, oplus, overdrive, pdcharm, pentium, pentium inside, skoool, sound mark, the journey inside, vtune, xeon, and xeon inside are trademark s of intel corporation in the u.s. and other countries. *other names and brands may be claimed as the property of others. copyright ? 2007, intel corporation. all rights reserved.
intel ? 81341 and 81342 i/o processors december 2007 datasheet order number: 315039-003US 3 contentsintel ? 81341 and 81342 contents 1.0 introduction .............................................................................................................. 7 1.1 about this document........................................................................................... 7 1.1.1 terminology ............................................................................................ 7 1.1.2 other relevant documents ........................................................................ 7 2.0 features ....................................................................................................................9 2.1 intel ? 81341 and intel ? 81342 i/o processors features........................................... 9 2.1.1 host interface........................................................................................ 11 2.1.2 internal busses ...................................................................................... 12 2.1.3 application dma controllers ..................................................................... 12 2.1.4 address translation unit ......................................................................... 12 2.1.5 messaging unit ...................................................................................... 12 2.1.6 ddr2 memory controller ......................................................................... 13 2.1.7 sram memory controller......................................................................... 13 2.1.8 peripheral bus interface .......................................................................... 13 2.1.9 i 2 c bus interface units ........................................................................... 13 2.1.10 uart units ............................................................................................ 13 2.1.11 interrupt controller unit.......................................................................... 13 2.1.12 xsi system controller............................................................................. 14 2.1.13 inter-processor communication................................................................ 14 2.1.14 timers .................................................................................................. 14 2.1.15 gpio .................................................................................................... 14 3.0 package information ............................................................................................... 15 3.1 package introduction ......................................................................................... 15 3.2 functional signal definitions ............................................................................... 15 3.2.1 signal pin descriptions ............................................................................ 15 4.0 electrical specifications ........................................................................................... 64 4.1 v ccpll pin requirements .................................................................................... 66 4.2 targeted dc specifications ................................................................................. 67 4.3 targeted ac specifications ................................................................................. 69 4.3.1 clock signal timings............................................................................... 69 4.3.2 ddr2 sdram interface signal timings...................................................... 72 4.3.3 peripheral bus interface signal timings ..................................................... 73 4.3.4 i 2 c/smbus interface signal timings.......................................................... 74 4.3.5 pci bus interface signal timings .............................................................. 75 4.3.6 pci express* differential transmitter (tx) output specifications ................... 76 4.3.7 pci express* differential receiver (rx) input specifications ......................... 78 4.3.8 boundary scan test signal timings .......................................................... 79 4.4 ac timing waveforms........................................................................................ 80
intel ? 81341 and 81342contents intel ? 81341 and 81342 i/o processors datasheet december 2007 4 order number: 315039-003US figures 1 intel? 81341 i/o processor functional block diagram (single processor ).........................10 2 intel? 81342 i/o processor functional block diagram (two processor) ...........................11 3 1357-lead fcbga package (top and bottom views) .....................................................36 4 intel? 81341 and 81342 i/o processors ballout package top (left side) ......................38 5 intel? 81341 and 81342 i/o processors ballout package top (right side) ....................39 6 intel? 81341 and 81342 i/o processors ballout package bottom (left side) ................40 7 intel? 81341 and 81342 i/o processors ballout package bottom (right side) ........... ...41 8v cc3p3pllx low-pass filter..........................................................................................66 9v cc1p2plld , v cc1p2pllp low-pass filter .........................................................................66 10 clock timing measurement waveforms........................................................................80 11 output timing measurement waveforms .....................................................................80 12 input timing measurement waveforms........................................................................81 13 i 2 c interface signal timings ......................................................................................81 14 ddr2 sdram write timings ......................................................................................82 15 dqs falling edge output access time to/from m_ck rising edge ................................. ...82 16 ddr2 sdram read timings .......................................................................................83 17 ac test load for all signals except pci, pci-express and ddr2 ......................................83 18 ac test load for ddr2 sdram signals........................................................................83 19 pci/pci-x tov(max) rising edge ac test load ............................................................84 20 pci/pci-x tov(max) falling edge ac test load............................................................84 21 pci/pci-x tov(min) ac test load ..............................................................................84 22 transmitter test load (100 ? diff load) ......................................................................84 23 transmitter eye diagram...........................................................................................85 24 receiver eye opening (differential).............................................................................85 25 pbi output timings...................................................................................................86 26 pbi external device timings (flash) ............................................................................87
intel ? 81341 and 81342 i/o processors december 2007 datasheet order number: 315039-003US 5 contentsintel ? 81341 and 81342 tables 1 pin description nomenclature .................................................................................... 15 2 ddr2 sdram signals ............................................................................................... 16 3 peripheral bus interface signals................................................................................. 18 4 compact pci hot swap signals .................................................................................. 19 5 pci bus signals ....................................................................................................... 20 6 pci express* signals ................................................................................................ 23 7 interrupt signals...................................................................................................... 24 8i 2 c and sm bus signals ............................................................................................ 25 9 uart signals........................................................................................................... 26 10 miscellaneous signals ............................................................................................... 28 11 power and ground signals......................................................................................... 29 12 reset strap signals .................................................................................................. 30 13 functional pin mode behavior .................................................................................... 33 14 intel? 81341 and 81342 i/o processors 1357-lead packagealphabetical ball listings .... 42 15 intel? 81341 and 81342 i/o processors 1357-lead packagealphabetical signal listings . 53 16 absolute maximum ratings ....................................................................................... 64 17 operating conditions ................................................................................................ 65 18 dc characteristics.................................................................................................... 67 19 i cc characteristics.................................................................................................... 68 20 pci clock timings .................................................................................................... 69 21 pci express* clock timings ....................................................................................... 70 22 ddr2 output clock timings....................................................................................... 71 23 ddr2 sdram signal timings ..................................................................................... 72 24 peripheral bus interface signal timings....................................................................... 73 25 i 2 c/smbus signal timings ......................................................................................... 74 26 pci signal timings ................................................................................................... 75 27 pci express* rx input specifications .......................................................................... 76 28 pci express* tx output specifications ........................................................................ 77 29 pci express* rx input specifications .......................................................................... 78 30 boundary scan test signal timings ............................................................................ 79 31 ac measurement conditions ...................................................................................... 83
intel ? 81341 and 81342contents intel ? 81341 and 81342 i/o processors datasheet december 2007 6 order number: 315039-003US revision history date revision description december 2007 003 revised for 4 gb memory support. march 2007 002 updated legal page 2 . edited text in section 2.1.2 . revise pcixcap description in ta b le 5 . updated ta b l e 1 8 for cgp, cpcix, cddr2 and lpin values. revised ta b l e 1 7 for tcase (tc) maximum value to 100c. revised figure 27 . october 2006 001 initial release
intel ? 81341 and 81342 i/o processors december 2007 datasheet order number: 315039-003US 7 introductionintel ? 81341 and 81342 1.0 introduction 1.1 about this document this document is a reference guide for the external architecture of the intel ? 81341 and 81342 i/o processors (also known as the 81341 and 81342). 1.1.1 terminology to aid the discussion of the intel ? 81341 and 81342 i/o processors architecture, the following terminology is used: downstream at or toward a pci bus with a higher number (after configuration) word 16 bits of data dword 32 bits of data qword 64 bits of data host processor processor located upstream from the intel ? 81341 and 81342 i/o processors local processor intel xscale ? processor within the intel ? 81341 and 81342 i/o processors local bus intel ? 81341 and 81342 i/o processors internal bus local memory memory subsystem on the intel xscale ? processor, ddr2 sdram or peripheral bus interface busses upstream at or toward a pci bus with a lower number (after configuration) 1.1.2 other relevant documents 1. intel xscale ? microarchitecture developers manual (order number 273473)intel corporation 2. pci local bus specification , revision 2.3pci special interest group 3. pci hot-plug specification, revision 1.0pci special interest group 4. pci bus power management interface specification , revision 1.1pci special interest group 5. pci express specification , revision 1.0apci special interest group
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december 2007 datasheet order number: 315038-003us 9 featuresintel ? 81341 and 81342 2.0 features 81341 and 81342 i/o processors are a single- or dual-function pci device that integrates one or two intel xscale ? processor(s) with intelligent peripherals including a pci bus bridge. the 81341 and 81342 i/o processors also support two internal busses: north xsi bus and south xsi bus. with the two internal busses, transactions can take place simultaneously on each bus. the north xsi bus provides one or two intel xscale ? processor(s) with low-latency access to either the ddr2 sdram memory controller or the on-chip sram memory controller. peripherals that generate large burst transactions are located on the south xsi bus, thus allowing the two intel xscale ? processors exclusive access to the north xsi bus. 81341 and 81342 i/o processors consolidate the following features into a single system: ? pciClocal memory bus address translation unit, function 0 programming interface ? messaging unit, function 0 programming interface ? application direct memory access (dma) controller (including offload for up to a 16-source xor operation) ? peripheral bus interface unit ? integrated ddr2 memory controller ? integrated sram memory controller ? two programmable timers per intel xscale ? processor ? watchdog timer per intel xscale ? processor ? three i 2 c bus interface units ? two serial port units ? sixteen general-purpose input/output (gpio) ports ? internal north busCsouth bus bridge it is an integrated processor that addresses the needs of intelligent i/o storage applications and helps reduce intelligent i/o system costs. 2.1 intel ? 81341 and 81342 i/o processors features figure 1 shows the intel? 81341 i/o processor single-processor block diagram. figure 2 shows the intel? 81342 i/o processor two-processor block diagram.
intel ? 81341 and 81342features datasheet december 2007 10 order number: 315038-003us figure 1. intel? 81341 i/o processor functional block diagram (single processor) pci - x or pci - e intel? 81341 i/ o processor 16 - bit i /f i 2 c bus 7 2- b i t i/f serial bus bridge multi - port ddr ii sdram memory controller three application dma channels host interface (atu, , chap ) multi - port sram memory controller two uarts three i 2 c bus interface apb pbi unit (flash) intel xscale core ( core id = 0h ) 512k l 2 cache timers interrupt controller smbus unit smbus 128 - bit south internal bus 128 - bit north internal bus pci - e host interface (atu , chap )
december 2007 datasheet order number: 315038-003us 11 featuresintel ? 81341 and 81342 note: the subsections that follow give a brief overview of each feature. refer to the appropriate chapter in the intel ? 81341 and 81342 i/o processors developers manual for full technical descriptions. 2.1.1 host interface 81341 and 81342 i/o processors can be set up as either a single or dual-function pci device, providing pci-x or pci express* interface or both pci-x and pci express* interfaces. the pci interface is selected as a reset option. each function is independently controlled and provides the tpmi interface. intel ? 81341 and 81342 i/o processors are a single-function pci device that provides either a pci-x or pci express* host interface. the address translation unit (atu) and the messaging unit (mu) provide the programming interface between the host processor and the intel ? 81341 and 81342 i/o processors. when pci-x 1.0b is selected as the upstream (host) i/o interface, pci express* is available as a private (not visible to the host), downstream i/o interface. likewise, when pci express* is selected as the upstream i/o interface, pci-x 1.0b is available as a private, downstream i/o interface. the selection of the upstream i/o interface is a reset strap option. figure 2. intel? 81342 i/o processor functional block diagram (two processor) pci-x or pci-e intel? 81342 i/o processor 16-bit i/f i 2 c bus 72-bit i/f serial bus bridge multi-port ddr ii sdram memory controller three application dma channels host interface (atu, tpmi, chap) multi-port sram memory controller two uarts three i 2 c bus interface apb pbi unit (flash) intel xscale core (coreid = 0h) 512k l2 cache timers intel xscale core (coreid = 1h) 512k l2 cache inter-core interrupt interrupt controller timers inter-core interrupt interrupt controller smbus unit smbus 128-bit south internal bus 128-bit north internal bus pci-e host interface (atu, tpmis, chap)
intel ? 81341 and 81342features datasheet december 2007 12 order number: 315038-003us 2.1.2 internal busses the 81341 and 81342 i/o processors are built around two internal busses: north internal bus and south internal bus. the two busses use the same bus protocol. the north internal bus is 128 bits wide and operates at 400 mhz. the north bus connects the two intel xscale ? processors, which have direct access to the ddr2 sdram and sram. the north xsi bus is designed to provide the two intel xscale ? processors with low-latency access. the south internal bus is 128 bits wide and operates at 400 mhz. the south xsi bus provides the data paths for burst transactions generated by the dmas. the south xsi bus internal address and data busses are parity-protected on a byte-wise basis. agents on the south xsi bus can generate and check address and data parity. the point-to- point interfaces between the agents and the ddr2 and sram memory controllers are also parity-protected on a byte-wise basis. 2.1.3 application dma controllers there are three application dma controllers. the application dma controller is dual- portedwith one of its ports connected to the south xsi bus and the other port to the ddr2 sdram memory controller. this application dma controller allows low-latency, high-throughput data transfers between pci bus agents and the ddr2 memory. the dma controller also allows data transfer between ddr2 memory. the dma controller supports chaining and unaligned data transfers. it is programmable through the intel xscale ? processor and the host processor. in addition to simple data transfers, the adma performs xor operations with up to 16 sources. 2.1.4 address translation unit the address translation unit (atu) allows pci transactions direct access to the 81341 and 81342 i/o processors local memory. the atu provides interface for the raid controller pci function. the atu supports transactions between pci address space and the 81341 and 81342 i/o processors address space. address translation is controlled through programmable registers accessible from both the pci interface and the intel xscale ? processor. dual access to registers allows flexibility in mapping the two address spaces. the atu also supports the following extended capability configuration headers: 1. power management header, as defined by pci bus power management interface specification , revision 1.1. 2. message signaled interrupt capability structure, as specified in pci local bus specification , revision 2.3. 3. pci-x capabilities list item, as specified in the pci-x addendum to the local bus specification, revision 1.0b. 2.1.5 messaging unit the messaging unit (mu) provides data transfer between the pci system and the 81341 and 81342 i/o processors. it uses interrupts to notify each system when new data arrives. the mu has four messaging mechanisms: message registers, doorbell registers, circular queues, and index registers. each allows a host processor or external pci device and the 81341 and 81342 i/o processors to communicate through message passing and interrupt generation. the mu, in conjunction with the atu, exists as the pci interface for pci function 0 when function 0 is set up as a raid controller.
december 2007 datasheet order number: 315038-003us 13 featuresintel ? 81341 and 81342 2.1.6 ddr2 memory controller the ddr2 memory controller allows direct control of the 400/533 mhz ddr2 sdram memory subsystem. it features programmable chip selects and support for error- correction codes (ecc). the ddr2 memory controller is multi-ported with the following interfaces: south internal bus, adma controllers, north internal bus. the memory controller interface configuration support includes unbuffered dimms, registered dimms, and discrete ddr2 sdram devices. 2.1.7 sram memory controller the sram memory controller allows direct control of a 1.0 mbyte sram memory subsystem. it supports error correction codes (ecc). the sram is used to store firmware code, i/o exchange contexts and for general-purpose data storage. 2.1.8 peripheral bus interface the peripheral bus interface unit is a data communication path to the flash memory components or other peripherals of a 81341 and 81342 i/o processors hardware system. the pbi includes support for either 8- or 16-bit devices. to perform these tasks at high bandwidth, the bus features a burst-transfer capability which allows successive 8/16-bit data transfers. 2.1.9 i 2 c bus interface units there are three i 2 c (inter-integrated circuit) bus interface units that allow the intel xscale ? processor to serve as a master and slave device residing on the i 2 c bus. the i 2 c0 allows the i/o processor to interface to a storage enclosure processor (sep). the bus allows the 81341 and 81342 i/o processors to interface to other i 2 c peripherals and microcontrollers for system management functions. for more information, refer to i 2 c peripherals for microcontrollers (philips semiconductor) 1 . 2.1.10 uart units the 81341 and 81342 i/o processors includes two uart units. the uart units allow the two intel xscale ? processors to serve as a master and slave device residing on the uart bus. the uart units use a serial bus consisting of a two-pin interface. uart0 allows the 81341 and 81342 i/o processors to interface to a console port for debugging. also refer to the national semiconductor* 16550 device specification 2 . 2.1.11 interrupt controller unit each intel xscale ? processor supports an interrupt controller unit (icu). the icu aggregates interrupt sources both external and internal sources of the 81341 and 81342 i/o processors to the intel xscale ? processor. the icu supports high- performance interrupt processing with direct interrupt service routine vector generation on a per-source basis. each source has programmability for masking, processor interrupt input, and priority. 2.1.12 xsi system controller each xsi bus (north and south) employs an xsi system controller. the xsi system controller observes all the address or data bus requests from requestors and completors connected to the xsi bus. the xsi system controller handles xsi address 1. http://www.semiconductors.philips.com/buses/i2c/ 2. http://www.national.com/pf/pc/pc16550d.html
intel ? 81341 and 81342features datasheet december 2007 14 order number: 315038-003us bus arbitration, xsi data bus arbitration, framing address bus cycles, and framing data bus cycles. the xsi system controller provides the shared address and shared data paths from/to units. 2.1.13 inter-processor communication each intel xscale ? processor can interrupt or issue a reset to the second intel xscale ? processor. each processor can generate up to 32 interrupts to the second processor. 2.1.14 timers the 81341 and 81342 i/o processors support two programmable 32-bit timers per processor. the 81341 and 81342 i/o processors also support one watchdog timer per processor. 2.1.15 gpio the 81341 and 81342 i/o processors includes sixteen general-purpose i/o (gpio) pins.
december 2007 datasheet order number: 315038-003us 15 package informationintel ? 81341 and 81342 3.0 package information 3.1 package introduction the intel ? 81341 and intel ? 81342 i/o processors is offered in a 1357-ball fcbga5 package. 3.2 functional signal definitions this section defines the pins and signals. 3.2.1 signal pin descriptions table 1. pin description nomenclature symbol description i input pin only o output pin only i/o pin can be either an input or an output od open-drain pin pwr power pin gnd ground pin pin must be connected as described sync (...) synchronous. signal meets timings relative to a clock. ? sync (p): synchronous to p_clkin ? sync (m): synchronous to m_ck[2:0] / m_ck#[2:0] ? sync (t): synchronous to tck async asynchronous. inputs can be asynchronous relative to all clocks. all asynchronous signals are level-sensitive. r/w indicates read or write capability. rst (p) the pin is reset with warm_rst# or p_rst# . rst (m) the pin is reset with m_rst# . m_rst# is asserted when the memory subsystem is reset. rst (pb) the pin is reset with pb_rstout# . pb_rstout# is asserted when the peripheral bus interface subsystem is reset. rst (t) the pin is reset with trst# . actlow the pin is an active-low signal. diff the pin is a differential signal pair. ? p at the end of a differential pin name indicates positive. ? n at the end of a differential pin name indicates negative.
intel ? 81341 and 81342package information datasheet december 2007 16 order number: 315038-003us table 2. ddr2 sdram signals (sheet 1 of 2) name count type description m_ck[2:0] , m_ck#[2:0] 6 o diff memory clockout: is used to provide the three differential clock pairs to the unbuffered dimm for the external sdram memory subsystem. registered dimms use only the m_ck[0] / m_ck#[0] pair, which drives the input to the on-dimm pll. m_rst# 1 o async actlow memory reset: indicates that the memory subsystem has been reset. it is used to re-initialize registered dimms. ma[14:0] a 14 o sync (m) rst (m) memory address bus: carries the multiplexed row and column addresses to the sdram memory banks. auto-precharge is not supported. ba[2:0] 3 o sync (m) rst (m) sdram bank address: controls which of the internal banks to read or write. ba[1:0] are used for 512 mbit technology memory. ba[2:0] are used for 1 gbit technology memory. ras# 1 o sync (m) rst (m) actlow sdram row address strobe: indicates the presence of a valid row address on the multiplexed address bus ma[13:0] . cas# 1 o sync (m) rst (m) actlow sdram column address strobe: indicates the presence of a valid column address on the multiplexed address bus ma[13:0] . we# 1 o sync (m) rst (m) actlow sdram write enable: indicates whether the current memory transaction is a read or write operation. cs[1:0]# 2 o sync (m) rst (m) actlow sdram chip select: enables the sdram devices for a memory access. one for each physical bank. cke[1:0] 2 o sync (m) rst (m) sdram clock enable enables: the clocks for the sdram memory. deasserting places the sdram in self-refresh mode. one for each physical bank. dq[63:0] 64 i/o sync (m) rst (m) sdram data bus: carries 64-bit data to and from memory. during the data cycle, read or write data is present on one or more contiguous bytes. during write operations, unused pins drive to determinate values. cb[7:0] 8 i/o sync (m) rst (m) sdram ecc check bits: carry the 8-bit ecc code to and from memory during data cycles. dqs[8:0] , dqs#[8:0] 18 i/o sync (m) rst (m) diff sdram data strobes: carry differential or single-ended strobe signals, output in write mode, and input in read mode for source synchronous data transfer. dm[8:0] 9 o sync (m) rst (m) sdram data mask: controls which bytes on the data bus are to be written. when dm[8:0] is asserted, the sdram devices do not accept valid data from the byte lanes. m_vref 1i sdram voltage reference: is used to supply the input switching reference voltage for the memory input signals. odt[1:0] 2 o sync (m) rst (m) on-die termination: is used to turn on sdram on-die termination during writes.
december 2007 datasheet order number: 315038-003us 17 package informationintel ? 81341 and 81342 m_cal[0] 1o memory calibration: connected to an external calibration resistor. memory output drivers reference the resistor to dynamically adjust drive strength to compensate for temperature and voltage variations. this pin connected through a 24.9 ohm 1% resistor to ground. m_cal[1] 1o memory calibration: connected to an external calibration resistor. memory output drivers reference the resistor to dynamically adjust odt resistance to compensate for temperature and voltage variations. this pin connected through a 301 ohm 1% resistor to ground. to t a l 1 3 5 a. ma[14] was added for 4gb memory support. when 4gb memory is not used this pin is nc. table 2. ddr2 sdram signals (sheet 2 of 2) name count type description
intel ? 81341 and 81342package information datasheet december 2007 18 order number: 315038-003us table 3. peripheral bus interface signals name count type description a[24:0] 25 o rst (pb) peripheral address bus: carries the address bits for the current access. the pbi interface can address up to 32 mbytes. d[15:0] 16 i/o rst (pb) peripheral data bus: carries read or write data to and from memory. during write operations to 8-bit wide memory regions, the pbi drives unused bus pins to determinate values. poe# 1 o rst (pb) actlow peripheral output enable: indicates whether bus access is write or read with respect to i/o processor and is valid during entire bus access. this pin can be used to control output enable on a peripheral device. 0 = read 1 = write pwe# 1 o rst (pb) actlow peripheral write enable: indicates to the peripheral device whether or not to write data to the addressed space. this pin can be used to control the write enable on the peripheral device. 0 = write 1 = read pce[1:0]# 2 o rst (pb) actlow peripheral chip enable: specifies which of the two memory address ranges are associated with the current bus access. the pin remains valid during the entire bus access. note: these pins must be pulled up to v cc3p3 with external 8.2k ohm 5%, 1/16 w resistors for proper operation. pb_rstout# 1 o actlow peripheral bus reset out: can be used to reset the peripheral device. it has the same timing as the internal bus reset. to t a l 4 6
december 2007 datasheet order number: 315038-003us 19 package informationintel ? 81341 and 81342 table 4. compact pci hot swap signals name count type description hs_enum# 1 od rst (p) actlow hot swap event: conditionally asserted to notify system host that either a board has been freshly inserted or is about to be extracted. this signal informs the system host that the configuration of the system has changed. the system host then performs any necessary maintenance such as installing or quiesing a device driver. hs_lstat 1 i rst (p) hot swap latch status: input indicating state of the ejector switch. 0 = indicates the ejector switch is closed. 1 = indicates the ejector switch is open. if compact pci hot swap not supported, tie this signal low. hs_led_out 1 o rst (p) hot swap led output: outputs a logic one to illuminate the hot swap blue led. hs_freq[1:0] / cr_freq[1:0] 2 i/o rst (p) hot swap frequency: in hot swap mode, these pins are inputs, determining the bus frequency and mode during a pci-x hot swap event. these are valid only when pcix_ep# =0 and hs_sm# =0. 00 =133 mhz pci-x 01 =100 mhz pci-x 10 = 66 mhz pci-x 11 = 33 or 66 mhz. pci (frequency depends on p_m66en ) central resource frequency: while in central resource mode, these pins are outputs, which control the external pci-x clock generator. these are valid only when pcix_ep# =1. 00 = 133 mhz 01 =100 mhz 10 =66 mhz 11 =33 mhz ? these pins have internal pull-ups. to t a l 5
intel ? 81341 and 81342package information datasheet december 2007 20 order number: 315038-003us table 5. pci bus signals (sheet 1 of 3) name count type description p_ad[63:32] 32 i/o sync (p) rst (p) pci address/data: is the upper 32 bits of the pci data bus driven during the data phase. p_ad[31:0] 32 i/o sync (p) rst (p) pci address/data: is the multiplexed pci address and lower 32 bits of the data bus. p_cbe[7]# 1 i/o sync (p) rst (p) actlow pci bus command and byte enables: are multiplexed on the same pci pins. during the address phase, they define the bus command. during the data phase, they are used as byte enables. p_cbe[6]# 1 i/o sync (p) rst (p) actlow pci bus command and byte enables: are multiplexed on the same pci pins. during the address phase, they define the bus command. during the data phase, they are used as byte enables. p_cbe[5]# 1 i/o sync (p) rst (p) actlow pci bus command and byte enables: are multiplexed on the same pci pins. during the address phase, they define the bus command. during the data phase, they are used as byte enables. p_cbe[4]# 1 i/o sync (p) rst (p) actlow pci bus command and byte enables: are multiplexed on the same pci pins. during the address phase, they define the bus command. during the data phase, they are used as byte enables. p_cbe[3]# 1 i/o sync (p) rst (p) actlow pci bus command and byte enables: are multiplexed on the same pci pins. during the address phase, they define the bus command. during the data phase, they are used as byte enables. p_cbe[2]# 1 i/o sync (p) rst (p) actlow pci bus command and byte enables: are multiplexed on the same pci pins. during the address phase, they define the bus command. during the data phase, they are used as byte enables. p_cbe[1]# 1 i/o sync (p) rst (p) actlow pci bus command and byte enables: are multiplexed on the same pci pins. during the address phase, they define the bus command. during the data phase, they are used as byte enables. p_cbe[0]# 1 i/o sync (p) rst (p) actlow pci bus command and byte enables: are multiplexed on the same pci pins. during the address phase, they define the bus command. during the data phase, they are used as byte enables. p_par64 1 i/o sync (p) rst (p) pci bus upper dword parity is even parity across p_ad[63:32] and p_cbe_#[7:4]. p_req64# 1 i/o sync (p) rst (p) actlow pci bus request 64-bit transfer indicates the attempt of a 64-bit transaction on the pci bus. when the target is 64-bit capable, the target acknowledges the attempt with the assertion of p_ack64_#. p_ack64# 1 i/o sync (p) rst (p) actlow pci bus acknowledge 64-bit transfer indicates that the device has positively decoded its address as the target of the current access and the target is willing to transfer data using the full 64-bit data bus. p_par 1 i/o sync (p) rst (p) pci bus parity is even parity across p_ad[31:0] and p_cbe_#[3:0]. p_frame# 1 i/o sync (p) rst (p) actlow pci bus cycle frame is asserted to indicate the beginning and duration of an access.
december 2007 datasheet order number: 315038-003us 21 package informationintel ? 81341 and 81342 p_irdy# 1 i/o sync (p) rst (p) actlow pci bus initiator ready indicates the initiating agents ability to complete the current data phase of the transaction. during a write, it indicates that valid data is present on the address/data bus. during a read, it indicates that the processor is ready to accept the data. p_trdy# 1 i/o sync (p) rst (p) actlow pci bus target ready indicates the target agents ability to complete the current data phase of the transaction. during a read, it indicates that valid data is present on the address/data bus. during a write, it indicates that the target is ready to accept the data. p_stop# 1 i/o sync (p) rst (p) actlow pci bus stop indicates a request to stop the current transaction on the pci bus. p_devsel# 1 i/o sync (p) rst (p) actlow pci bus device select is driven by a target agent that has successfully decoded the address. as an input, it indicates whether or not an agent has been selected. p_serr# 1 i/o od sync (p) rst (p) actlow pci bus system error is driven for address parity errors on the pci bus. p_rstout# 1 o async actlow pci reset out is based on p_rst# and warm_rst# . it brings pci-specific registers, sequencers, and signals to a consistent state. when either p_rst# or warm_rst# is asserted, it causes p_rstout# to assert and: ? pci output signals are driven to a known consistent state. ? pci bus interface output signals are three-stated. ? open-drain signals such as p_serr_# are floated. p_rstout# can be asynchronous to p_clk when asserted or deasserted. p_perr# 1 i/o sync (p) rst (p) actlow pci bus parity error is asserted when a data parity error occurs during a pci bus transaction. p_m66en 1i pci bus 66 mhz enable indicates the speed of the pci bus. when this signal is sampled high, the pci bus speed is 66 mhz; when low, the bus speed is 33 mhz. p_idsel 1 i sync (p) pci bus initialization device select is used to select the intel ? 81341 and intel ? 81342 i/o processors during a configuration read or write. note: in central resource mode this pin must be pulled down to v ss with an external 4.7k ohm 5%, 1/16 w resistor for proper operation. p_gnt[0]# / p_req# 1 o sync (p) actlow pci bus grant: ? internal arbiter mode: this is one of four output grant signals from the internal arbiter. pci bus request: ? external arbiter mode: this is the output request signal for the atu. p_req[0]# / p_gnt# 1 i sync (p) rst (p) actlow pci bus request: ? internal arbiter mode: this is one of four input request signals to the internal arbiter. pci bus grant: ? external arbiter mode: this is the input grant signal to the atu. table 5. pci bus signals (sheet 2 of 3) name count type description
intel ? 81341 and 81342package information datasheet december 2007 22 order number: 315038-003us p_gnt[3:1]# 3 o sync (p) actlow pci bus grant: ? external arbiter mode: not used ? internal arbiter mode: these are three of four output grant signals from the internal arbiter. p_req[3:1]# 3 i sync (p) rst (p) actlow pci bus request: ? external arbiter mode: not used ? internal arbiter mode: these are three of four input request signals to the internal arbiter. p_pcixcap 1i pci-x capability: refer to the intel ? 81341 and intel ? 81342 i/o processors specification update for more details. p_bmi 1 o sync (p) rst (p) pci bus master indicator indicates that the i/o processor is mastering a transaction on the pci bus. p_cal[0] 1o pci calibration is connected to an external calibration resistor. the v ccvio pci output drivers reference the resistor to dynamically adjust the drive strength to compensate for voltage and temperature variations. this pin is connected through a 22.1 ohm 1% resistor to ground. p_cal[1] 1o pci calibration is connected to an external calibration resistor. the pci output drivers reference the resistor to dynamically adjust the odt resistance to compensate for voltage and temperature variations. this pin is connected through a 121 ohm 1% resistor to ground. p_cal[2] 1o pci calibration is connected to an external calibration resistor. the v cc3p3 pci output drivers reference the resistor to dynamically adjust the drive strength to compensate for voltage and temperature variations. this pin is connected through a 22.1 ohm 1% resistor to ground. p_clkin 1i pci bus input clock provides the ac timing reference for all pci transactions. p_clkout 1o pci bus output clock: when refclkn / refclkp are used, the i/o processor can generate the pci output clocks. this pin is then connected to p_clkin and trace length matched to p_clko[3:0] . p_clko[3:0] 4o pci bus output clocks: when refclkn / refclkp are used, the i/ o processor can generate the pci output clocks. these pins then provide the pci clocks to devices on the pci bus. to t a l 1 0 5 table 5. pci bus signals (sheet 3 of 3) name count type description
december 2007 datasheet order number: 315038-003us 23 package informationintel ? 81341 and 81342 table 6. pci express* signals name count type description refclkp , refclkn 2 i diff pci express* clock is the 100 mhz differential input reference clock for the pci express* interface. petp[7:0] , petn[7:0] 16 o diff pci express* transmit carries the differential output serial data and embedded clock for the pci express* interface. perp[7:0] , pern[7:0] 16 i diff pci express* receive carries the differential input serial data and embedded clock for the pci express* interface. pe_calp , pe_caln 2 i/o pci express* calibration pins are connected to an external calibration resistor. the pci express* output drivers can reference the resistor to dynamically adjust their slew rate and drive strength to compensate for voltage and temperature variations. a 1.4k ohm 1% resistor is connected between these two pins. to t a l 3 6
intel ? 81341 and 81342package information datasheet december 2007 24 order number: 315038-003us table 7. interrupt signals name count type description p_int[d:a]# / xint[3:0]# / gpio[11:8] 4 od i i/o async rst (p) actlow when pcix_ep# = 0: ? pci interrupt requests an interrupt from the central resource. the assertion and deassertion is asynchronous. a device asserts its xint[3:0]# / p_int[d:a]# line when requesting attention from its device driver. as soon as the xint[3:0]# / p_int[d:a]# signal is asserted, it remains asserted until the device driver clears the pending request. when pcix_ep# = 1: ? external interrupt requests are used by external devices to request interrupt service. these pins are level-detect inputs and are internally synchronized. these pins go to the xint[3:0]# inputs of the interrupt controller. the interrupt controller can steer the interrupt to either the fiq or the irq internal interrupt input of the intel xscale ? processor. general purpose i/o pins can be selected on a per-pin basis as general-purpose inputs or outputs. the default mode is a general- purpose input. xint[7:4]# / gpio[15:12] 4 i i/o async actlow external interrupt requests are used by external devices to request interrupt service. these pins are level-detect and are internally synchronized. these pins go to the xint[7:4]# inputs of the interrupt controller. the interrupt controller can steer the interrupt to either the fiq or the irq internal interrupt input of the intel xscale ? processor. general purpose i/o pins can be selected on a per-pin basis as general-purpose inputs or outputs. the default mode is a general- purpose input. gpio[7:0] / xint[15:8]# / pmonout 8 i/o i o async rst (p) general purpose i/o pins can be selected on a per-pin basis as general-purpose inputs or outputs. the default mode is a general- purpose input. external interrupts are used by external devices to request interrupt service. these pins are level-detect and are internally synchronized. these pins go to the xint[15:8]# inputs of the interrupt controller. these interrupts are dedicated to the intel xscale ? processor. to enable a given pin as an interrupt, it needs to be unmasked in the intctl[3:0] register. performance monitor out: the pmon unit output indicator will generate a signal on the gpio[7] pin when enabled in the pmonen register. when enabled it will override the normal gpio[7] function. hpi# 1 i async actlow high-priority interrupt causes a high-priority interrupt to the i/o processor. this pin is level-detect only and is internally synchronized. nmi0# 1 i async actlow non-maskable interrupt causes a non-maskable data abort to the intel xscale ? processor 0 in the i/o processor. this pin is falling edge-detect only and is internally synchronized. nmi1# 1 i async actlow non-maskable interrupt causes a non-maskable data abort to the intel xscale ? processor 1 in the i/o processor. this pin is falling edge-detect only and is internally synchronized. note: this signal not applicable to the 81341 processor. to t a l 1 9
december 2007 datasheet order number: 315038-003us 25 package informationintel ? 81341 and 81342 table 8. i 2 c and sm bus signals name count type description scl0 1 i/o od i 2 c 0 clock provides synchronous operation of the i 2 c bus. sda0 1 i/o od i 2 c 0 data is used for data transfer and arbitration of the i 2 c bus. scl1 1 i/o od i 2 c 1 clock provides synchronous operation of the i 2 c bus. sda1 1 i/o od i 2 c 1 data is used for data transfer and arbitration of the i 2 c bus. scl2 1 i/o od i 2 c 2 clock provides synchronous operation of the i 2 c bus. sda2 1 i/o od i 2 c 2 data is used for data transfer and arbitration of the i 2 c bus. smbclk 1 i/o od sm bus clock provides synchronous operation of the sm bus. smbdat 1 i/o od sm bus data is used for data transfer and arbitration of the bus. to t a l 8 note: open drain outputs require an external pull-up resistor to pull up the signal to 3.3 v. the value of the pull-up resistor depends on the bus loading.
intel ? 81341 and 81342package information datasheet december 2007 26 order number: 315038-003us table 9. uart signals (sheet 1 of 2) name count type description u0_rxd 1 i async uart 0 serial input: serial data input from device pin to the receive shift register. u0_txd 1 o async uart 0 serial output: composite serial data output to the communications link-peripheral, modem, or data set. the txd signal is set to the marking (logic 1) state upon a reset operation. u0_cts# 1 i actlow async uart 0 clear to send: when low, this pin indicates that the receiving uart is ready to receive data. when the receiving uart deasserts cts# high, the transmitting uart must stop transmission to prevent overflow of the receiving uart buffer. the cts# signal is a modem-status input whose condition can be tested by the host processor or by the uart when in autoflow mode as described below: ? non-autoflow mode: when not in autoflow mode, bit[4] (cts) of the modem status register (msr) indicates the state of cts#. bit[4] is the complement of the cts# signal. bit[0] (dcts) of the modem status register indicates whether the cts# input has changed state since the previous reading of the modem status register. cts# has no effect on the transmitter. the user can program the uart to interrupt the processor when dcts changes state. the programmer can then stall the outgoing data stream by starving the transmit fifo or disabling the uart with the ier register. note: when uart transmission is stalled by disabling the uart, the user does not receive an msr interrupt when cts# reasserts. this is because disabling the uart also disables interrupts. to work around this, the user can use auto cts in autoflow mode, or program the cts# pin to interrupt. ? autoflow mode: in autoflow mode, the uart transmit circuity checks the state of cts# before transmitting each byte. when cts# is high, no data is transmitted. u0_rts# 1 o actlow async uart 0 request to send: this bit indicates to the remote device whether the uart is ready to receive data. when this bit is low, the uart is ready to receive data. a reset operation sets this signal to its inactive (high) state. loop mode operation holds this signal in its inactive state. ? non-autoflow mode: the rts# output signal can be asserted by setting bit[1] (rts) of the modem control register to 1. the rts bit is the complement of the rts# signal. ? autoflow mode: rts# is automatically asserted by the autoflow circuitry when the receive buffer exceeds its programmed threshold. it is deasserted when enough bytes are removed from the buffer to lower the data level back to the threshold. u1_rxd 1 i async uart 1 serial input: serial data input from the device pin to the receive shift register.
december 2007 datasheet order number: 315038-003us 27 package informationintel ? 81341 and 81342 u1_txd 1 o async uart 1 serial output: composite serial data output to the communications link-peripheral, modem, or data set. the txd signal is set to the marking (logic 1) state upon a reset operation. u1_cts# 1 i actlow async uart 1 clear to send: when low, this pin indicates that the receiving uart is ready to receive data. when the receiving uart deasserts cts# high, the transmitting uart must stop transmission to prevent overflow of the receiving uart buffer. the cts# signal is a modem-status input whose condition can be tested by the host processor or by the uart when in autoflow mode as described below: ? non-autoflow mode: when not in autoflow mode, bit[4] (cts) of the modem status register (msr) indicates the state of cts#. bit[4] is the complement of the cts# signal. bit[0] (dcts) of the modem status register indicates whether the cts# input has changed state since the previous reading of the modem status register. cts# has no effect on the transmitter. the user can program the uart to interrupt the processor when dcts changes state. the programmer can then stall the outgoing datastream by starving the transmit fifo or disabling the uart with the ier register. note: when uart transmission is stalled by disabling the uart, the user does not receive an msr interrupt when cts# reasserts. this is because disabling the uart also disables interrupts. to get around this, the user can use auto cts in autoflow mode, or program the cts# pin to interrupt. ? autoflow mode: in autoflow mode, the uart transmit circuity checks the state of cts# before transmitting each byte. when cts# is high, no data is transmitted. u1_rts# 1 o actlow async uart 1 request to send: this bit indicates to the remote device whether the uart is ready to receive data. when low, the uart is ready to receive data. a reset operation sets this signal to its inactive (high) state. loop mode operation holds this signal in its inactive state. ? non-autoflow mode: the rts# output signal can be asserted by setting bit[1] (rts) of the modem control register to 1. the rts bit is the complement of the rts# signal. ? autoflow mode: rts# is automatically asserted by the autoflow circuitry when the receive buffer exceeds its programmed threshold. it is deasserted when enough bytes are removed from the buffer to lower the data level back to the threshold. to t a l 8 table 9. uart signals (sheet 2 of 2) name count type description
intel ? 81341 and 81342package information datasheet december 2007 28 order number: 315038-003us table 10. miscellaneous signals name count type description tck 1i test clock provides clock input for ieee 1149.1 boundary scan testing (jtag). state information and data are clocked into the device on the rising clock edge, and data is clocked out on the falling clock edge. tdi 1 i sync (t) test data input is the jtag serial input pin. tdi is sampled on the rising edge of tck, during the shift-ir and shift-dr states of the test access port. this signal has a weak internal pull-up to ensure proper operation when this pin is not being driven. tdo 1 o sync (t) rst (t) test data output is the serial output pin for the jtag feature. tdo is driven on the falling edge of tck during the shift-ir and shift-dr states of the test access port. at other times, tdo floats. the behavior of tdo is independent of other resets. trst# 1 i async actlow test reset asynchronously resets the test access port controller function of ieee 1149 boundary scan testing (jtag). this pin has a weak internal pull-up. note: this pin must be tied low when not used. tms 1 i sync (t) test mode select is sampled on the rising edge of tck to select the operation of the test logic for ieee 1149 boundary scan testing. this pin has a weak internal pull-up. nc 106 i/o no connect: pins have no usable function and must not be connected to any signal, power, or ground. p_rst# 1 i async actlow cold reset is used to asynchronously reset the i/o processor when it is low. this signal must be asserted whenever the power supplies are outside of the specified ranges. ? registers are reset to default values. ? pins are driven to known states. ? sticky configuration bits are reset. warm_rst# 1i async actlow warm reset is the same as a cold reset, except sticky configuration bits are not reset. this pin should only be used when the sticky bit functionality is required. in this scenario, the warm_rst# pin must be tied to the system reset pci_rst# signal while the p_rst# pin can be tied to the system power good signal. if the sticky bit functionality is not required, the warm_rst# pin should not be used and must be tied to vcc. when the pci express interface is used as an endpoint, the pci express inband hot reset mechanism can also be used to provide the sticky bit functionality. note: driving warm_rst# using any other methods than suggested above may result in unpredictable behavior of the device. thermda 1 i thermal diode anode is the anode of the thermal diode. thermdc 1 o thermal diode cathode is the cathode of the thermal diode. pur1 1i pull-up required 1: this pin must be pulled up to v cc3p3 with an external 8.2k ohm 5%, 1/16 w resistor for proper operation. to t a l 1 1 6
december 2007 datasheet order number: 315038-003us 29 package informationintel ? 81341 and 81342 table 11. power and ground signals name count type description v cc1p2pllp 1 pwr v cc pll pci-x: ball connected to a 1.2 v filtered board supply. provides power to pll that controls the pci-x logic and interface. v cc1p2plld 1 pwr v cc pll ddr: ball connected to a 1.2 v filtered board supply. provides power to the pll that controls the ddr2 sdram interface and processor digital logic. v cc3p3pllx 1 pwr v cc pll x: ball to be connected to a 3.3 v filtered board supply. this pin provides power to a voltage regulator, which supplies power to the pll that controls the intel xscale ? processor and xsi processor logic. vsspllp 1 gnd v ss pll pci-x: ball connected to capacitor of the v cc1p2pllp filter. vssplld 1 gnd v ss pll ddr2 sdram: ball connected to capacitor of v cc1p2plld filter. vsspllx 1 gnd v ss pll x: ball connected to capacitor of v cc3p3pllx filter. v cc1p2 204 pwr 1.2 v power: balls to be connected to a 1.2 v board power plane. these pins provide power to the processor logic. v cc1p2ae 8 pwr 1.2 v power: balls to be connected to a 1.2 v board power plane. these pins provide power to the pci express* analog logic. v cc1p2e 6 pwr 1.2 v power: balls to be connected to a 1.2 v board power plane. these pins provide power to the pci express* digital logic. v cc1p2x 119 pwr 1.2 v power: balls to be connected to a 1.2 v board power plane. these pins provide power to the intel xscale ? processors. v ccvio 21 pwr vio power: balls to be connected to a 3.3 v board power plane. these pins provide 3.3 v power to the pci-x i/os. v cc1p8 36 pwr 1.8 v power: balls to be connected to a 1.8 v board power plane. these pins provide power to the ddr2 sdram interface i/os. v cc1p8e 14 pwr 1.8 v power: balls to be connected to a 1.8 v board power plane. these pins provide power to the pci express* interface i/os. v cc3p3 42 pwr 3.3 v power: balls to be connected to a 3.3 v board power plane. these pins provide power to the pbi, miscellaneous pins, and pci-x i/os in mode 1. v ss 403 gnd ground: balls to be connected to a board ground plane. v sse 20 gnd pci express* ground: balls connected to a board ground plane. to t a l 8 8 0
intel ? 81341 and 81342package information datasheet december 2007 30 order number: 315038-003us table 12. reset strap signals (sheet 1 of 3) name count type description boot_width_8# 1 reset strap pbi boot bus width: sets the default bus width for the pbi memory boot window. 0 = 8 bits wide 1 = 16 bits wide (default mode) note: muxed onto signal a[0] . df_sel[2:0] 3 reset strap device function select: these straps select the number of storage ports assigned to each function within the intel ? 81341 and intel ? 81342 i/o processors. note: df_sel[2] muxed onto signal a[9] note: df_sel[1] muxed onto signal a[8] note: df_sel[0] muxed onto signal a[7] see the device function select of the intel l? 81341 and intel l? 81342 i/o processors developer's manual for additional details. cfg_cycle_en# 1 reset strap configuration cycle enable: determines whether pci interface retries configuration cycles until host lockout bit is cleared in all enabled tpmi functions (tcfgr[5]). 0 = configuration cycles enabled 1 = configuration retry enabled (default mode) ? pci-x interface: configuration cycles are claimed and terminated with a retry status. ? pci express* interface: configuration requests result in a completion tlp with configuration retry status (crs). note: muxed onto signal a[1] hold_x0_in_rst# 1 reset strap hold intel xscale ? microprocessor 0 in reset: determines whether the intel xscale ? microprocessor number 0 is held in reset until the reset bit is cleared in the pci configuration and status register. 0 = hold in reset 1 = do not hold in reset (default mode) note: muxed onto signal a[2] hold_x1_in_rst# 1 reset strap hold intel xscale ? microprocessor 1 in reset: determines whether the intel xscale ? microprocessor number 1 is held in reset until the reset bit is cleared in the pci configuration and status register. 0 = hold in reset 1 = do not hold in reset (default mode) note: muxed onto signal a[3] note: this signal not applicable to the 81341 processor. mem_freq[1:0] 2 reset strap memory frequency: determines frequency at which ddr2 memory subsystem runs. 00 = reserved 01 =reserved 10 =533 mhz 11 =400 mhz (default mode) note: mem_freq[1] muxed onto signal a[5] note: mem_freq[0] muxed onto signal a[4] ext_arb# 1 reset strap external arbiter: determines whether the pci interface enables the integrated arbiter, or use an external arbiter. 0 = external arbiter 1 = internal arbiter (default mode) note: muxed onto signal a[6] interface_sel_pcix# 1 reset strap 0 = pci-x is active 1 = pci express is active (default mode) when both interfaces are active, this strap selects the atu that is function 0 in the internal address map. note: muxed onto signal a[10] pcix_ep# 1 reset strap pci-x end point: determines whether the pci-x interface operates as an endpoint or a central resource. 0 = endpoint 1 = central resource (default mode) note: muxed onto signal a[11] note: setting both pcix_ep# and pcie_rc# to endpoint is unsupported.
december 2007 datasheet order number: 315038-003us 31 package informationintel ? 81341 and 81342 pcie_rc# 1 reset strap pci-e root complex: determines whether pci express* interface operates as an endpoint or a root complex. 0 = root complex 1 = endpoint (default mode) note: muxed onto signal a[12] setting both pcix_ep# and pcie_rc# to endpoint is unsupported. smb_a5 , smb_a3 , smb_a2 , smb_a1 4 reset strap sm bus address: maps to address bit[5], bit[3], bit[2], and bit[1] where bits[7:0] represent address smbus slave port responds to when access is attempted. 0 = address bit is low 1 = address bit is high (default mode) note: smb_a5 muxed onto signal a[16] note: smb_a3 muxed onto signal a[15] note: smb_a2 muxed onto signal a[14] note: smb_a1 muxed onto signal a[13] pcix_pullup# 1 reset strap pci-x pull up: determines whether pci interface has on-die pull-ups enabled. these may be used for the central resource bus keepers. 0 = enable pci pull-up resistors 1 = disable pci pull-up resistors (default mode) note: muxed onto signal a[17] pcix_32bit# 1 reset strap 32-bit pci-x bus: indicates width of the pci-x bus to pci-x status register. enables pull-ups for upper half of bus when in 32-bit mode. 0 = 32-bit wide pci-x bus 1 = 64-bit wide pci-x bus (default mode) note: muxed onto signal a[18] pcixm1_100# 1 reset strap pci-x mode 1 100 mhz enable: in central resource mode, this bit limits pci-x bus to 100 mhz while in mode 1: 0 = limit pci-x mode 1 to 100 mhz 1 = 133 mhz enabled (default mode) note: muxed onto signal a[19] hs_sm# 1 reset strap hot swap startup mode: in end point mode, this bit determines whether hot swap mode is enabled. 0 = hot swap mode enabled 1 = hot swap mode disabled (default mode) note: muxed onto signal a[21] fw_timer_off# 1 reset strap firmware timer off: disables 400 ms firmware timer for development and debug. when enabled, timer automatically clears configuration cycle retry (ccr) bit in pcsr after 400 ms regardless of processor state. when disabled, ccr bit functions as normal based on state of cfg_cycle_en# pin at rising edge of p_rst#. 0 = firmware timer disabled 1 = firmware timer enabled (default mode) note: muxed onto signal a[22] controller_only# 1 reset strap controller-only enable: 0 = controller only, raid disabled 1 = raid enabled (default mode) note: muxed onto signal a[23] lk_dn_rst_bypass# 1 reset strap link down reset bypass: disables the full chip reset that would normally be caused by a link down or hot reset. 0 = do not reset on link down 1 = reset on link down (default mode) note: muxed onto signal a[24] table 12. reset strap signals (sheet 2 of 3) name count type description
intel ? 81341 and 81342package information datasheet december 2007 32 order number: 315038-003us clk_src_pcie# 1 reset strap clock source pci-e: selects pci express* refclk pair as the input clock to the plls that control most internal logic. 0 = source clock is refclkp / refclkn 1 = source clock is p_clkin (default mode) note: when p_clko[3:0] are used this pin must be pulled low. note: muxed onto signal pwe# to t a l 2 5 reset strap signals are latched on the rising edge of p_rst# . all reset strap signals are internally pulled to logic 1 by default. an external 4.7k ohm 5%, 1/16 w pull-down resistor is required to force a logic 0 on these pins. table 12. reset strap signals (sheet 3 of 3) name count type description
december 2007 datasheet order number: 315038-003us 33 package informationintel ? 81341 and 81342 table 13. functional pin mode behavior (sheet 1 of 4) pin b o u n d a r y s c a n h i g h z r e s e t ( e n d p o i n t ) r e s e t ( c e n t r a l r e s o u r c e ) n o r m a l 3 2 - b i t s d r a m p c i x _ 3 2 b i t # p c i x _ p u l l u p # w h e n o n l y p c i - x i n t e r f a c e a c t i v e w h e n o n l y p c i e x p r e s s * i n t e r f a c e a c t i v e m_ck[2:0] , m_ck#[2:0] zvovovoCCCCC m_rst# z0*0*voCCCCC ma[14:0] a zvovovoCCCCC ba[2:0] zvovovoCCCCC ras# zvovovoCCCCC cas# zvovovoCCCCC we# zvovovoCCCCC cs[1:0]# zvovovoCCCCC cke[1:0] z0*0*voCCCCC dq[63:32] zz*z*vbzCCCC dq[31:0] zz*z*vbCCCCC cb[7:0] zz*z*vbCCCCC dqs[8] , dqs#[8] zz*z*vbCCCCC dqs[7:4] , dqs#[7:4] zz*z*vbzCCCC dqs[3:0] , dqs#[3:0] zz*z*vbCCCCC dm[8] zvo*vo*voCCCCC dm[7:4] zvo*vo*voCCCCC dm[3:0] zvo*vo*voCCCCC m_vref CaiaiaiCCCCC odt[1:0] z0*0*voCCCCC m_cal[1:0] zz*z*aoCCCCC a[24:0] zhhvoCCCCC d[15:0] zhhvbCCCCC poe# zhhvoCCCCC pwe# zhhvoCCCCC pb_rstout# z00voCCCCC pce[1:0]# zhhvoCCCCC hs_enum# zzzvoCCCCC hs_lstat CviviviCCCCC hs_led_out z11voCCCCC hs_freq[1:0] / cr_freq[1:0] zhhhCCCCC notes: 1 = driven to v cc 0 = driven to v ss x = driven to unknown state id = the input is disabled. h = pulled up to v cc pd = pull-up disabled l = pulled down to v ss odt = on die termination gnd = tie to ground. ea = external arbiter mode ia = internal arbiter mode z = output, pull-up/down disabled vb = acts like a valid bidirectional pin vo = a valid output level is driven. vi = need to drive a valid input level. ao = analog output level ai = analog input level * = after power fail sequence completes - = unaffected by this mode a. ma[14] is only needed for 4gb memory support. when 4gb memory is not used this pin is nc.
intel ? 81341 and 81342package information datasheet december 2007 34 order number: 315038-003us p_ad[63:32] zzzvbChhCh p_ad[31:0] zz0vbCCCCh p_cbe[7:4]# zzzvbChhCh p_cbe[3:0]# zz0vbCCCCh p_par64 zzzvbChhCh p_req64# zvi0vbC C h C h p_ack64# zzzvbCChCh p_par zz0vbCCCCh p_frame# zvivovbCChCh p_irdy# zvivovbCChCh p_trdy# zvivovbCChCh p_stop# zvivovbCChCh p_devsel# zvivovbCChCh p_serr# zzzvbCChCh p_rstout# z00voCCCCvo p_perr# zvivovbCChCh p_m66en CviviviCCCCh p_idsel CviviviCCCCh p_gnt[0]# / p_req# z z (ea) h (ia) z (ea) h (ia) voCCCCh p_req[0]# / p_gnt# C vi (ea) h (ia) vi (ea) h (ia) vi (ea) h (ia) CCCCh p_gnt[3:1]# zhhvoCCCCh p_req[3:1]# ChhhCCCCh p_clkin CviviviCCCCgnd p_clkout zzvovoCCCCz p_clko[3:0] zzvovoCCCCz p_pcixcap CaiaiaiCCCCgnd p_bmi zvovovoCCCCvo p_cal[2:0] zaoaoaoCCCCvo refclkp , refclkn C vivivi C C C gnd/ vi C petp[7:0] , petn[7:0] CzzvoCCCzC table 13. functional pin mode behavior (sheet 2 of 4) pin b o u n d a r y s c a n h i g h z r e s e t ( e n d p o i n t ) r e s e t ( c e n t r a l r e s o u r c e ) n o r m a l 3 2 - b i t s d r a m p c i x _ 3 2 b i t # p c i x _ p u l l u p # w h e n o n l y p c i - x i n t e r f a c e a c t i v e w h e n o n l y p c i e x p r e s s * i n t e r f a c e a c t i v e notes: 1 = driven to v cc 0 = driven to v ss x = driven to unknown state id = the input is disabled. h = pulled up to v cc pd = pull-up disabled l = pulled down to v ss odt = on die termination gnd = tie to ground. ea = external arbiter mode ia = internal arbiter mode z = output, pull-up/down disabled vb = acts like a valid bidirectional pin vo = a valid output level is driven. vi = need to drive a valid input level. ao = analog output level ai = analog input level * = after power fail sequence completes - = unaffected by this mode a. ma[14] is only needed for 4gb memory support. when 4gb memory is not used this pin is nc.
december 2007 datasheet order number: 315038-003us 35 package informationintel ? 81341 and 81342 perp[7:0] , pern[7:0] CididviCCCzC pe_calp C aoaoao C C C z C pe_caln C aoaoao C C C z C p_int[d:a]# / xint[3:0]# z z/vi z/vi vb C C h C C xint[7:4]# CviviviCCCCC gpio[7:0] / xint[15:8]# / pmonout zvivivbCCCCC hpi# CviviviCCCCC nmi0# CviviviCCCCC nmi1# CviviviCCCCC scl0 zzzvbCCCCC sda0 zzzvbCCCCC scl1 zzzvbCCCCC sda1 zzzvbCCCCC scl2 zzzvbCCCCC sda2 zzzvbCCCCC smbclk zzzvbCCCCC smbdat zzzvbCCCCC u0_rxd CviviviCCCCC u0_txd z11voCCCCC u0_cts# CviviviCCCCC u0_rts# z11voCCCCC u1_rxd CviviviCCCCC u1_txd z11voCCCCC u1_cts# CviviviCCCCC u1_rts# z11voCCCCC tck CviviviCCCCC tdi ChhhCCCCC table 13. functional pin mode behavior (sheet 3 of 4) pin b o u n d a r y s c a n h i g h z r e s e t ( e n d p o i n t ) r e s e t ( c e n t r a l r e s o u r c e ) n o r m a l 3 2 - b i t s d r a m p c i x _ 3 2 b i t # p c i x _ p u l l u p # w h e n o n l y p c i - x i n t e r f a c e a c t i v e w h e n o n l y p c i e x p r e s s * i n t e r f a c e a c t i v e notes: 1 = driven to v cc 0 = driven to v ss x = driven to unknown state id = the input is disabled. h = pulled up to v cc pd = pull-up disabled l = pulled down to v ss odt = on die termination gnd = tie to ground. ea = external arbiter mode ia = internal arbiter mode z = output, pull-up/down disabled vb = acts like a valid bidirectional pin vo = a valid output level is driven. vi = need to drive a valid input level. ao = analog output level ai = analog input level * = after power fail sequence completes - = unaffected by this mode a. ma[14] is only needed for 4gb memory support. when 4gb memory is not used this pin is nc.
intel ? 81341 and 81342package information datasheet december 2007 36 order number: 315038-003us tdo CzzvoCCCCC trst# ChhhCCCCC tms ChhhCCCCC p_rst# CviviviCCCCC warm_rst# CviviviCCCCC nc -/zz/hz/hz/hCCCCC thermda CaiaiaiCCCCC thermdc CaoaoaoCCCCC table 13. functional pin mode behavior (sheet 4 of 4) pin b o u n d a r y s c a n h i g h z r e s e t ( e n d p o i n t ) r e s e t ( c e n t r a l r e s o u r c e ) n o r m a l 3 2 - b i t s d r a m p c i x _ 3 2 b i t # p c i x _ p u l l u p # w h e n o n l y p c i - x i n t e r f a c e a c t i v e w h e n o n l y p c i e x p r e s s * i n t e r f a c e a c t i v e notes: 1 = driven to v cc 0 = driven to v ss x = driven to unknown state id = the input is disabled. h = pulled up to v cc pd = pull-up disabled l = pulled down to v ss odt = on die termination gnd = tie to ground. ea = external arbiter mode ia = internal arbiter mode z = output, pull-up/down disabled vb = acts like a valid bidirectional pin vo = a valid output level is driven. vi = need to drive a valid input level. ao = analog output level ai = analog input level * = after power fail sequence completes - = unaffected by this mode a. ma[14] is only needed for 4gb memory support. when 4gb memory is not used this pin is nc.
december 2007 datasheet order number: 315038-003us 37 package informationintel ? 81341 and 81342 figure 3. 1357-lead fcbga package (top and bottom views)
intel ? 81341 and 81342package information datasheet december 2007 38 order number: 315038-003us
intel ? 81341 and 81342 i/o processors december 2007 datasheet order number: 315039-003US 39 package informationintel ? 81341 and 81342 the following figures show the intel? 81341 and 81342 i/o processors ballout diagrams: ? figure 4, intel? 81341 and 81342 i/o processors ballout package top (left side) on page 40 ? figure 5, intel? 81341 and 81342 i/o processors ballout package top (right side) on page 41 ? figure 6, intel? 81341 and 81342 i/o processors ballout package bottom (left side) on page 42 ? figure 7, intel? 81341 and 81342 i/o processors ballout package bottom (right side) on page 43 the following tables show the intel? 81341 and 81342 i/o processors ball and signal listings: ? table 14, intel? 81341 and 81342 i/o processors 1357-lead package alphabetical ball listings on page 44 ? table 15, intel? 81341 and 81342 i/o processors 1357-lead package alphabetical signal listings on page 55
intel ? 81341 and 81342package information intel ? 81341 and 81342 i/o processors datasheet december 2007 40 order number: 315039-003US figure 4. intel? 81341 and 81342 i/o processors ballout package top (left side) abcdefghj k lmnprtuvw 37 vss dq[63] dqs[7] dqs# [7] dq[57] dq[56] dq[60] dq[43] dq[47] dqs[5] dqs# [5] dq[41] dq[40] dq[44] cb[2] cb[6] dqs# [8] 36 vss dq[59] dq[58] dq[62] vss dm[7] dq[61] vss vss dq[42] dq[46] vss dm[5] dq[45] vss cb[3] cb[7] dqs[8] 35 vss nc dq[51] dq[50] dqs[6] dqs# [6] dm[6] dq[53] dq[52] dq[35] dq[34] dqs[4] dqs# [4] dm[4] dq[37] dq[36] m_ck# [2] vss dm[8] 34 nc nc vss dq[55] dq[54] vss dq[49] dq[48] vss vss dq[39] dq[38] vss dq[33] dq[32] vss m_ck [2] m_ck# [0] m_ck [0] 33 nc nc ma[14] a nc vss odt[1] cs#[1] ma[13] odt[0] cas# we# vss cs#[0] ras# ba[0] ma[10] ba[1] ma[0] vss 32 nc nc nc nc nc vcc3 p3 vcc3 p3 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 31 nc nc nc nc nc nc vcc3 p3 vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss 30 nc vss nc vss nc nc vcc3 p3 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x 29 nc nc nc nc nc nc vcc3 p3 vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vsspllx therm da nc 28 nc nc nc nc nc nc vcc3 p3 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x therm dc vcc1 p2x 27 nc vss nc vss nc nc vcc3 p3 vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss 26 nc nc nc nc nc nc vcc3 p3 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x 25 nc nc nc nc nc nc vcc3 p3 vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss 24 vss vss vss vss vcc1 p2 vcc1 p2 vcc1 p2 vss vcc1 p2 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x 23 nc nc nc nc vcc1 p2 vcc1 p2 vcc1 p2 vcc1 p2 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss 22 nc nc nc nc vcc1 p2 vcc1 p2 vcc1 p2 vss vcc1 p2 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x 21 vss vss vss vss nc nc nc vss vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 20 nc nc nc nc nc nc nc vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 19 nc nc nc nc vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 18 vss vss vss vss vcc1 p8 vcc1 p8 vcc1 p8 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 17 nc nc nc nc vcc1 p2 vss vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 16 nc nc nc nc nc nc nc vss vss vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 15 vss vss vss vss nc nc nc vss vcc1 p2 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 14 nc nc nc nc vss vcc1 p2 vss vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 13 nc nc nc nc vcc1 p2 vss vcc1 p2 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 12 vss vss vss vss vss vcc1 p2 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 11 gpio[1] gpio[3] gpio[7] gpio[5] gpio[6] vcc3 p3 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vsspllp vcc1 p2pllp vss vcc1 p2 vss vcc1 p2 vss 10 gpio[0] vss gpio[2] vss gpio[4] vcc3 p3 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 9 xint# [1] xint# [3] xint# [5] xint# [4] xint# [7] vcc3 p3 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 8 xint# [2] xint# [0] xint# [6] nmi0# hs_led_ out vcc3 p3 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 7 hs_enu m# vss hpi# vss nmi1# vcc3 p3 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 6 u0_ rts# u0_ rxd hs_lstat hs_freq[ 1] hs_freq[ 0] vcc3 p3 vcc3 p3 vccvio vcc3 p3 vcc3 p3 vccvio vccvio vcc3 p3 vccvio vcc3 p3 vcc3 p3 vccvio vcc3 p3 vcc3 p3 5 u0_ cts# u0_ txd u1_ rxd nc vcc3 p3 p_cal [0] p_gnt#[ 3] vccvio p_gnt#[ 0] p_ad [31] vccvio p_ad [26] p_idsel vccvio p_ad [16] p_trdy# vccvio p_ad [13] p_ad [9] 4 u1_ cts# u1_ txd u1_ rts# vss warm_r st# p_bmi vss p_ req#[3] p_gnt#[ 1] vss p_ad [30] p_ad [24] vss p_ad [20] p_frame # vss p_ par p_ad [11] vss 3 vss p_clko [3] p_clko [2] p_cal [2] nc p_cal [1] p_ req#[2] p_gnt#[ 2] nc p_ad [27] p_ad [28] p_ad [23] p_ad [22] p_ad [18] p_devse l# p_stop# p_ad [15] p_ad [12] p_ cbe# [0] 2 vss p_clko [0] p_ clkout vss p_rst# vss nc nc vss p_ad [25] p_ad [21] vss p_ cbe# [2] p_pcixc ap vss p_ cbe# [1] p_ad [10] vss 1 vss p_clkin p_clko [1] p_rstout # nc p_ req#[1] p_ req#[0] p_ad [29] p_ cbe# [3] p_ad [19] p_ad [17] p_irdy# p_perr# p_serr# p_ad [14] p_m66e n vss abcdefghj k lmnprtuvw a. ma[14] only needed for 4gb memory support, otherwise this pin is nc.
intel ? 81341 and 81342 i/o processors december 2007 datasheet order number: 315039-003US 41 package informationintel ? 81341 and 81342 figure 5. intel? 81341 and 81342 i/o processors ballout package top (right side) y aaabacadaeafagahajakalamanaparatau cb[1] cb[0] dq[27] dq[31] dqs[3] dqs# [3] dq[25] dq[24] dq[28] dq[11] dq[15] dqs[1] dqs# [1] dq[9] dm[1] vss 37 cb[5] cb[4] vss dq[26] dq[30] vss dm[3] dq[29] vss vss dq[10] dq[14] vss dq[8] dq[13] dq[12] vss 36 vss m_ck [1] dq[19] dq[18] dqs[2] dqs# [2] dm[2] dq[21] dq[20] dq[3] dq[2] dqs[0] dqs# [0] dm[0] dq[5] dq[4] m_cal [0] vss 35 ma[2] m_ck# [1] vss dq[23] dq[22] vss dq[17] dq[16] vss vss dq[7] dq[6] vss dq[1] dq[0] vss m_cal [1] vss 34 ma[1] ma[3] ma[4] ma[6] vss ma[5] ma[8] ma[7] ma[9] ma[11] ma[12] vss ba[2] cke[0] cke[1] m_rst# m_vref vss 33 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 32 vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc3 p3 vcc3 p3 vss tck vss trst# 31 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vcc3 p3 vcc3 p3 vcc3 p3 tdo tms tdi 30 vcc3 p3pllx vss vcc1 p2x vssplld vcc1 p2plld vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc3 p3 scl1sda2sda1scl0 smb clk 29 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vcc3 p3 scl2 vss sda0 vss smb dat 28 vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vcc1 p2x vcc1 p2x vcc1 p2x vcc1 p2x vcc1 p2x vcc1 p2x vcc1 p2x vcc1 p2x vcc1 p2x 27 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vcc1 p8e vcc1 p8e vcc1 p8e vcc1 p8e vcc1 p8e vcc1 p8e 26 vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p8e vcc1 p8e vsse vsse vsse vsse 25 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vcc1 p2ae vcc1 p8e petn [7] petp [7] pern [7] perp [7] 24 vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2 vss vcc1 p2ae vcc1 p8e petn [6] petp [6] pern [6] perp [6] 23 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2 vss vcc1 p2 vcc1 p2ae vcc1 p8e vsse vsse vsse vsse 22 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2ae vcc1 p8e petn [5] petp [5] pern [5] perp [5] 21 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 refclkp nc nc pe_ calp petn [4] petp [4] pern [4] perp [4] 20 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss refclkn nc nc pe_ caln vsse vsse vsse vsse 19 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vcc1 p2ae vcc1 p8e petn [3] petp [3] pern [3] perp [3] 18 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2ae vcc1 p8e petn [2] petp [2] pern [2] perp [2] 17 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vcc1 p2ae vcc1 p2e vsse vsse vsse vsse 16 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2ae vcc1 p2e petn [1] petp [1] pern [1] perp [1] 15 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vcc1 p2e vcc1 p2e petn [0] petp [0] pern [0] perp [0] 14 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2e vcc1 p2e vsse vsse vsse vsse 13 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vcc1 p2 vcc1 p2 vcc1 p2 vcc1 p2 vcc1 p2 vcc1 p2 12 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc3 p3 pce# [1] a[21] a[19] a[18] a[22] 11 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vcc3 p3 a[20] vss pce# [0] vss a[13] 10 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc3 p3 nc a[9] a[12] a[8] a[14] 9 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vcc3 p3 pur1 a[10] pb_ rstout# a[1] a[6] 8 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc3 p3 a[11] vss a[15] vss a[2] 7 vccvio vccvio vcc3 p3 vccvio vccvio vcc3 p3 vccvio vccvio vcc3 p3 vccvio vccvio vcc3 p3 vcc3 p3 d[15] a[16] a[17] a[3] a[7] 6 p_ad [4] vccvio p_ cbe# [7] p_ par64 vccvio p_ad [56] p_ad [52] vccvio p_ad [44] p_ad [40] vccvio p_ad [32] d[10] vcc3 p3 d[9] d[4] a[4] a[5] 5 p_ad [6] p_ad [0] vss p_ cbe# [5] p_ad [60] vss p_ad [54] p_ad [48] vss p_ad [42] p_ad [36] vss poe# d[2] vss d[3] d[8] d[1] 4 p_ad [5] p_ad [2] p_ req64# p_ad [63] p_ad [62] p_ad [58] p_ad [51] p_ad [50] p_ad [46] p_ad [39] p_ad [38] p_ad [34] pwe# d[12] d[11] a[23] d[0] vss 3 p_ad [7] p_ad [1] vss p_ cbe# [4] p_ad [59] vss p_ad [53] p_ad [47] vss p_ad [41] p_ad [35] vss d[14] d[6] d[5] a[0] vss 2 p_ad [8] p_ad [3] p_ ack64# p_ cbe# [6] p_ad [61] p_ad [57] p_ad [55] p_ad [49] p_ad [45] p_ad [43] p_ad [37] p_ad [33] a[24] d[7] d[13] vss 1 y aaabacadaeafagahajakalamanaparatau
intel ? 81341 and 81342package information intel ? 81341 and 81342 i/o processors datasheet december 2007 42 order number: 315039-003US figure 6. intel? 81341 and 81342 i/o processors ballout package bottom (left side) au at ar ap an am al ak aj ah ag af ae ad ac ab aa y w 37 vss dm[1] dq[9] dqs# [1] dqs[1] dq[15] dq[11] dq[28] dq[24] dq[25] dqs# [3] dqs[3] dq[31] dq[27] cb[0] cb[1] dqs# [8] 36 vss dq[12] dq[13] dq[8] vss dq[14] dq[10] vss vss dq[29] dm[3] vss dq[30] dq[26] vss cb[4] cb[5] dqs[8] 35 vss m_cal [0] dq[4] dq[5] dm[0] dqs# [0] dqs[0] dq[2] dq[3] dq[20] dq[21] dm[2] dqs# [2] dqs[2] dq[18] dq[19] m_ck [1] vss dm[8] 34 vss m_cal [1] vss dq[0] dq[1] vss dq[6] dq[7] vss vss dq[16] dq[17] vss dq[22] dq[23] vss m_ck# [1] ma[2] m_ck [0] 33 vss m_vref m_rst# cke[1] cke[0] ba[2] vss ma[12] ma[11] ma[9] ma[7] ma[8] ma[5] vss ma[6] ma[4] ma[3] ma[1] vss 32 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 31 trst# vss tck vss vcc3 p3 vcc3 p3 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss 30 tdi tms tdo vcc3 p3 vcc3 p3 vcc3 p3 vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x 29 smb clk scl0 sda1 sda2 scl1 vcc3 p3 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2plld vssplld vcc1 p2x vss vcc3 p3pllx nc 28 smb dat vss sda0 vss scl2 vcc3 p3 vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x 27 vcc1 p2x vcc1 p2x vcc1 p2x vcc1 p2x vcc1 p2x vcc1 p2x vcc1 p2x vcc1 p2x vcc1 p2x vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss 26 vcc1 p8e vcc1 p8e vcc1 p8e vcc1 p8e vcc1 p8e vcc1 p8e vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x 25 vsse vsse vsse vsse vcc1 p8e vcc1 p8e vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss 24 perp [7] pern [7] petp [7] petn [7] vcc1 p8e vcc1 p2ae vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x 23 perp [6] pern [6] petp [6] petn [6] vcc1 p8e vcc1 p2ae vss vcc1 p2 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss 22 vsse vsse vsse vsse vcc1 p8e vcc1 p2ae vcc1 p2 vss vcc1 p2 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x 21 perp [5] pern [5] petp [5] petn [5] vcc1 p8e vcc1 p2ae vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 20 perp [4] pern [4] petp [4] petn [4] pe_ calp nc nc refclkp vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 19 vsse vsse vsse vsse pe_ caln nc nc refclkn vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 18 perp [3] pern [3] petp [3] petn [3] vcc1 p8e vcc1 p2ae vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 17 perp [2] pern [2] petp [2] petn [2] vcc1 p8e vcc1 p2ae vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 16 vsse vsse vsse vsse vcc1 p2e vcc1 p2ae vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 15 perp [1] pern [1] petp [1] petn [1] vcc1 p2e vcc1 p2ae vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 14 perp [0] pern [0] petp [0] petn [0] vcc1 p2e vcc1 p2e vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 13 vsse vsse vsse vsse vcc1 p2e vcc1 p2e vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 12 vcc1 p2 vcc1 p2 vcc1 p2 vcc1 p2 vcc1 p2 vcc1 p2 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 11 a[22] a[18] a[19] a[21] pce# [1] vcc3 p3 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 10 a[13] vss pce# [0] vss a[20] vcc3 p3 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 9 a[14] a[8] a[12] a[9] nc vcc3 p3 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 8a[6]a[1] pb_ rstout# a[10] pur1 vcc3 p3 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 7 a[2] vss a[15] vss a[11] vcc3 p3 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 6 a[7] a[3] a[17] a[16] d[15] vcc3 p3 vcc3 p3 vccvio vccvio vcc3 p3 vccvio vccvio vcc3 p3 vccvio vccvio vcc3 p3 vccvio vccvio vcc3 p3 5 a[5] a[4] d[4] d[9] vcc3 p3 d[10] p_ad [32] vccvio p_ad [40] p_ad [44] vccvio p_ad [52] p_ad [56] vccvio p_ par64 p_ cbe# [7] vccvio p_ad [4] p_ad [9] 4 d[1] d[8] d[3] vss d[2] poe# vss p_ad [36] p_ad [42] vss p_ad [48] p_ad [54] vss p_ad [60] p_ cbe# [5] vss p_ad [0] p_ad [6] vss 3 vss d[0] a[23] d[11] d[12] pwe# p_ad [34] p_ad [38] p_ad [39] p_ad [46] p_ad [50] p_ad [51] p_ad [58] p_ad [62] p_ad [63] p_ req64# p_ad [2] p_ad [5] p_ cbe# [0] 2 vss a[0] d[5] d[6] d[14] vss p_ad [35] p_ad [41] vss p_ad [47] p_ad [53] vss p_ad [59] p_ cbe# [4] vss p_ad [1] p_ad [7] vss 1 vss d[13] d[7] a[24] p_ad [33] p_ad [37] p_ad [43] p_ad [45] p_ad [49] p_ad [55] p_ad [57] p_ad [61] p_ cbe# [6] p_ ack64# p_ad [3] p_ad [8] vss au at ar ap an am al ak aj ah ag af ae ad ac ab aa y w
intel ? 81341 and 81342 i/o processors december 2007 datasheet order number: 315039-003US 43 package informationintel ? 81341 and 81342 figure 7. intel? 81341 and 81342 i/o processors ballout package bottom (right side) vutrpnml k jhgfedcba cb[6] cb[2] dq[44] dq[40] dq[41] dqs# [5] dqs[5] dq[47] dq[43] dq[60] dq[56] dq[57] dqs# [7] dqs[7] dq[63] vss 37 cb[7] cb[3] vss dq[45] dm[5] vss dq[46] dq[42] vss vss dq[61] dm[7] vss dq[62] dq[58] dq[59] vss 36 vss m_ck# [2] dq[36] dq[37] dm[4] dqs# [4] dqs[4] dq[34] dq[35] dq[52] dq[53] dm[6] dqs# [6] dqs[6] dq[50] dq[51] nc vss 35 m_ck# [0] m_ck [2] vss dq[32] dq[33] vss dq[38] dq[39] vss vss dq[48] dq[49] vss dq[54] dq[55] vss nc nc 34 ma[0] ba[1] ma[10] ba[0] ras# cs#[0] vss we# cas# odt[0] ma[13] cs#[1] odt[1] vss nc ma[14] a nc nc 33 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc3 p3 vcc3 p3 nc nc nc nc nc 32 vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vcc3 p3 nc nc nc nc nc nc 31 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc3 p3 nc nc vss nc vss nc 30 therm da vsspllx vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vcc3 p3 nc nc nc nc nc nc 29 therm dc vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc3 p3 nc nc nc nc nc nc 28 vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vcc3 p3 nc nc vss nc vss nc 27 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc3 p3 nc nc nc nc nc nc 26 vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vcc3 p3 nc nc nc nc nc nc 25 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2 vss vcc1 p2 vcc1 p2 vcc1 p2 vss vss vss vss 24 vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2 vcc1 p2 vcc1 p2 vcc1 p2 nc nc nc nc 23 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2 vss vcc1 p2 vcc1 p2 vcc1 p2 nc nc nc nc 22 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vss nc nc nc vss vss vss vss 21 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss nc nc nc nc nc nc nc 20 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vcc1 p8 vcc1 p8 vcc1 p8 nc nc nc nc 19 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p8 vcc1 p8 vcc1 p8 vss vss vss vss 18 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vss vcc1 p2 nc nc nc nc 17 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vss vss nc nc nc nc nc nc nc 16 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vcc1 p2 vss nc nc nc vss vss vss vss 15 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vss vcc1 p2 vssncnc ncnc14 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vcc1 p2 vss vcc1 p2 nc nc nc nc 13 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vcc1 p2 vss vss vss vss vss 12 vcc1 p2 vss vcc1 p2 vss vcc1 p2pllp vsspllp vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc3 p3 gpio[6] gpio[5] gpio[7] gpio[3] gpio[1] 11 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vcc3 p3 gpio[4] vss gpio[2] vss gpio[0] 10 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc3 p3 xint# [7] xint# [4] xint# [5] xint# [3] xint# [1] 9 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vcc3 p3 hs_led_ out nmi0# xint# [6] xint# [0] xint# [2] 8 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc3 p3 nmi1# vss hpi# vss hs_enu m# 7 vcc3 p3 vccvio vcc3 p3 vcc3 p3 vccvio vcc3 p3 vccvio vccvio vcc3 p3 vcc3 p3 vccvio vcc3 p3 vcc3 p3 hs_freq[ 0] hs_freq[ 1] hs_lstat u0_ rxd u0_ rts# 6 p_ad [13] vccvio p_trdy# p_ad [16] vccvio p_idsel p_ad [26] vccvio p_ad [31] p_gnt#[ 0] vccvio p_gnt#[ 3] p_cal [0] vcc3 p3 nc u1_ rxd u0_ txd u0_ cts# 5 p_ad [11] p_ par vss p_frame # p_ad [20] vss p_ad [24] p_ad [30] vss p_gnt#[ 1] p_ req#[3] vss p_bmi warm_r st# vss u1_ rts# u1_ txd u1_ cts# 4 p_ad [12] p_ad [15] p_stop# p_devs el# p_ad [18] p_ad [22] p_ad [23] p_ad [28] p_ad [27] nc p_gnt#[ 2] p_ req#[2] p_cal [1] nc p_cal [2] p_clko [2] p_clko [3] vss 3 p_ad [10] p_ cbe# [1] vss p_pcixc ap p_ cbe# [2] vss p_ad [21] p_ad [25] vss nc nc vss p_rst# vss p_clkout p_clko [0] vss 2 p_m66e n p_ad [14] p_serr# p_perr# p_irdy# p_ad [17] p_ad [19] p_ cbe# [3] p_ad [29] p_ req#[0] p_ req#[1] nc p_rstout # p_clko [1] p_clkin vss 1 vutrpnml k jhgfedcba a. ma[14] only needed for 4gb memory support, otherwise this pin is nc.
intel ? 81341 and 81342package information intel ? 81341 and 81342 i/o processors datasheet december 2007 44 order number: 315039-003US table 14. intel? 81341 and 81342 i/o processors 1357-lead packagealphabetical ball listings (sheet 1 of 11) ball signal ball signal ball signal a1 C b7 vss c13 nc a2 C b8 xint#[0] c14 nc a3 vss b9 xint#[3] c15 vss a4 u1_cts# b10 vss c16 nc a5 u0_cts# b11 gpio[3] c17 nc a6 u0_rts# b12 vss c18 vss a7 hs_enum# b13 nc c19 nc a8 xint#[2] b14 nc c20 nc a9 xint#[1] b15 vss c21 vss a10 gpio[0] b16 nc c22 nc a11 gpio[1] b17 nc c23 nc a12 vss b18 vss c24 vss a13 nc b19 nc c25 nc a14 nc b20 nc c26 nc a15 vss b21 vss c27 nc a16 nc b22 nc c28 nc a17 nc b23 nc c29 nc a18 vss b24 vss c30 nc a19 nc b25 nc c31 nc a20 nc b26 nc c32 nc a21 vss b27 vss c33 ma[14] a a22 nc b28 nc c34 vss a23 nc b29 nc c35 dq[51] a24 vss b30 vss c36 dq[59] a25 nc b31 nc c37 vss a26 nc b32 nc d1 p_clkin a27 nc b33 nc d2 p_clkout a28 nc b34 nc d3 p_cal[2] a29 nc b35 nc d4 vss a30 nc b36 vss d5 nc a31 nc b37 C d6 hs_freq[1] a32 nc c1 vss d7 vss a33 nc c2 p_clko[0] d8 nmi0# a34 nc c3 p_clko[2] d9 xint#[4] a35 vss c4 u1_rts# d10 vss a36 C c5 u1_rxd d11 gpio[5] a37 C c6 hs_lstat d12 vss b1 C c7 hpi# d13 nc b2 vss c8 xint#[6] d14 nc b3 p_clko[3] c9 xint#[5] d15 vss b4 u1_txd c10 gpio[2] d16 nc b5 u0_txd c11 gpio[7] d17 nc b6 u0_rxd c12 vss d18 vss
intel ? 81341 and 81342 i/o processors december 2007 datasheet order number: 315039-003US 45 package informationintel ? 81341 and 81342 d19 nc e25 nc f31 nc d20 nc e26 nc f32 vcc3p3 d21 vss e27 nc f33 odt[1] d22 nc e28 nc f34 vss d23 nc e29 nc f35 dqs#[6] d24 vss e30 nc f36 vss d25 nc e31 nc f37 dqs#[7] d26 nc e32 nc g1 nc d27 vss e33 vss g2 vss d28 nc e34 dq[54] g3 p_req#[2] d29 nc e35 dqs[6] g4 vss d30 vss e36 dq[62] g5 p_gnt#[3] d31 nc e37 dqs[7] g6 vcc3p3 d32 nc f1 p_rstout# g7 vss d33 nc f2 p_rst# g8 vcc1p2 d34 dq[55] f3 p_cal[1] g9 vss d35 dq[50] f4 p_bmi g10 vcc1p2 d36 dq[58] f5 p_cal[0] g11 vss d37 dq[63] f6 vcc3p3 g12 vcc1p2 e1 p_clko[1] f7 vcc3p3 g13 vcc1p2 e2 vss f8 vcc3p3 g14 vss e3 nc f9 vcc3p3 g15 nc e4 warm_rst# f10 vcc3p3 g16 nc e5 vcc3p3 f11 vcc3p3 g17 vss e6 hs_freq[0] f12 vcc1p2 g18 vcc1p8 e7 nmi1# f13 vss g19 vcc1p8 e8 hs_led_out f14 vcc1p2 g20 nc e9 xint#[7] f15 nc g21 nc e10 gpio[4] f16 nc g22 vcc1p2 e11 gpio[6] f17 vss g23 vcc1p2 e12 vss f18 vcc1p8 g24 vcc1p2 e13 vcc1p2 f19 vcc1p8 g25 vcc3p3 e14 vss f20 nc g26 vcc3p3 e15 nc f21 nc g27 vcc3p3 e16 nc f22 vcc1p2 g28 vcc3p3 e17 vcc1p2 f23 vcc1p2 g29 vcc3p3 e18 vcc1p8 f24 vcc1p2 g30 vcc3p3 e19 vcc1p8 f25 nc g31 vcc3p3 e20 nc f26 nc g32 vcc3p3 e21 nc f27 nc g33 cs#[1] e22 vcc1p2 f28 nc g34 dq[49] e23 vcc1p2 f29 nc g35 dm[6] e24 vcc1p2 f30 nc g36 dm[7] table 14. intel? 81341 and 81342 i/o processors 1357-lead packagealphabetical ball listings (sheet 2 of 11) ball signal ball signal ball signal
intel ? 81341 and 81342package information intel ? 81341 and 81342 i/o processors datasheet december 2007 46 order number: 315039-003US g37 dq[57] j6 vcc3p3 k12 vss h1 p_req#[1] j7 vss k13 vcc1p2 h2 nc j8 vcc1p2 k14 vss h3 p_gnt#[2] j9 vss k15 vcc1p2 h4 p_req#[3] j10 vcc1p2 k16 vss h5 vccvio j11 vss k17 vcc1p2 h6 vccvio j12 vcc1p2 k18 vss h7 vcc1p2 j13 vss k19 vcc1p2 h8 vss j14 vcc1p2 k20 vss h9 vcc1p2 j15 vcc1p2 k21 vcc1p2 h10 vss j16 vss k22 vss h11 vcc1p2 j17 vss k23 vcc1p2x h12 vss j18 vcc1p2 k24 vss h13 vcc1p2 j19 vss k25 vcc1p2x h14 vss j20 vcc1p2 k26 vss h15 vss j21 vss k27 vcc1p2x h16 vss j22 vcc1p2 k28 vss h17 vcc1p2 j23 vss k29 vcc1p2x h18 vss j24 vcc1p2 k30 vss h19 vcc1p2 j25 vss k31 vcc1p2x h20 vss j26 vcc1p2x k32 vcc1p8 h21 vss j27 vss k33 cas# h22 vss j28 vcc1p2x k34 vss h23 vcc1p2 j29 vss k35 dq[35] h24 vss j30 vcc1p2x k36 vss h25 vcc1p2x j31 vss k37 dq[43] h26 vss j32 vcc1p8 l1 p_cbe#[3] h27 vcc1p2x j33 odt[0] l2 p_ad[25] h28 vss j34 vss l3 p_ad[28] h29 vcc1p2x j35 dq[52] l4 p_ad[30] h30 vss j36 vss l5 vccvio h31 vcc1p2x j37 dq[60] l6 vccvio h32 vcc1p8 k1 p_ad[29] l7 vss h33 ma[13] k2 vss l8 vcc1p2 h34 dq[48] k3 p_ad[27] l9 vss h35 dq[53] k4 vss l10 vcc1p2 h36 dq[61] k5 p_ad[31] l11 vss h37 dq[56] k6 vcc3p3 l12 vcc1p2 j1 p_req#[0] k7 vcc1p2 l13 vss j2 nc k8 vss l14 vcc1p2 j3 nc k9 vcc1p2 l15 vss j4 p_gnt#[1] k10 vss l16 vcc1p2 j5 p_gnt#[0] k11 vcc1p2 l17 vss table 14. intel? 81341 and 81342 i/o processors 1357-lead packagealphabetical ball listings (sheet 3 of 11) ball signal ball signal ball signal
intel ? 81341 and 81342 i/o processors december 2007 datasheet order number: 315039-003US 47 package informationintel ? 81341 and 81342 l18 vcc1p2 m24 vss n30 vcc1p2x l19 vss m25 vcc1p2x n31 vss l20 vcc1p2 m26 vss n32 vcc1p8 l21 vss m27 vcc1p2x n33 cs#[0] l22 vcc1p2x m28 vss n34 vss l23 vss m29 vcc1p2x n35 dqs#[4] l24 vcc1p2x m30 vss n36 vss l25 vss m31 vcc1p2x n37 dqs#[5] l26 vcc1p2x m32 vcc1p8 p1 p_irdy# l27 vss m33 vss p2 p_cbe#[2] l28 vcc1p2x m34 dq[38] p3 p_ad[18] l29 vss m35 dqs[4] p4 p_ad[20] l30 vcc1p2x m36 dq[46] p5 vccvio l31 vss m37 dqs[5] p6 vccvio l32 vcc1p8 n1 p_ad[17] p7 vcc1p2 l33 we# n2 vss p8 vss l34 dq[39] n3 p_ad[22] p9 vcc1p2 l35 dq[34] n4 vss p10 vss l36 dq[42] n5 p_idsel p11 vcc1p2pllp l37 dq[47] n6 vcc3p3 p12 vss m1 p_ad[19] n7 vss p13 vcc1p2 m2 p_ad[21] n8 vcc1p2 p14 vss m3 p_ad[23] n9 vss p15 vcc1p2 m4 p_ad[24] n10 vcc1p2 p16 vss m5 p_ad[26] n11 vsspllp p17 vcc1p2 m6 vccvio n12 vcc1p2 p18 vss m7 vcc1p2 n13 vss p19 vcc1p2 m8 vss n14 vcc1p2 p20 vss m9 vcc1p2 n15 vss p21 vcc1p2 m10 vss n16 vcc1p2 p22 vss m11 vcc1p2 n17 vss p23 vcc1p2x m12 vss n18 vcc1p2 p24 vss m13 vcc1p2 n19 vss p25 vcc1p2x m14 vss n20 vcc1p2 p26 vss m15 vcc1p2 n21 vss p27 vcc1p2x m16 vss n22 vcc1p2x p28 vss m17 vcc1p2 n23 vss p29 vcc1p2x m18 vss n24 vcc1p2x p30 vss m19 vcc1p2 n25 vss p31 vcc1p2x m20 vss n26 vcc1p2x p32 vcc1p8 m21 vcc1p2 n27 vss p33 ras# m22 vss n28 vcc1p2x p34 dq[33] m23 vcc1p2x n29 vss p35 dm[4] table 14. intel? 81341 and 81342 i/o processors 1357-lead packagealphabetical ball listings (sheet 4 of 11) ball signal ball signal ball signal
intel ? 81341 and 81342package information intel ? 81341 and 81342 i/o processors datasheet december 2007 48 order number: 315039-003US p36 dm[5] t5 p_trdy# u11 vss p37 dq[41] t6 vcc3p3 u12 vcc1p2 r1 p_perr# t7 vcc1p2 u13 vss r2 p_pcixcap t8 vss u14 vcc1p2 r3 p_devsel# t9 vcc1p2 u15 vss r4 p_frame# t10 vss u16 vcc1p2 r5 p_ad[16] t11 vcc1p2 u17 vss r6 vcc3p3 t12 vss u18 vcc1p2 r7 vss t13 vcc1p2 u19 vss r8 vcc1p2 t14 vss u20 vcc1p2 r9 vss t15 vcc1p2 u21 vss r10 vcc1p2 t16 vss u22 vcc1p2x r11 vss t17 vcc1p2 u23 vss r12 vcc1p2 t18 vss u24 vcc1p2x r13 vss t19 vcc1p2 u25 vss r14 vcc1p2 t20 vss u26 vcc1p2x r15 vss t21 vcc1p2 u27 vss r16 vcc1p2 t22 vss u28 vcc1p2x r17 vss t23 vcc1p2x u29 vsspllx r18 vcc1p2 t24 vss u30 vcc1p2x r19 vss t25 vcc1p2x u31 vss r20 vcc1p2 t26 vss u32 vcc1p8 r21 vss t27 vcc1p2x u33 ba[1] r22vcc1p2x t28vss u34m_ck[2] r23vss t29vcc1p2x u35m_ck#[2] r24 vcc1p2x t30 vss u36 cb[3] r25 vss t31 vcc1p2x u37 cb[2] r26 vcc1p2x t32 vcc1p8 v1 p_m66en r27 vss t33 ma[10] v2 p_ad[10] r28 vcc1p2x t34 vss v3 p_ad[12] r29 vss t35 dq[36] v4 p_ad[11] r30 vcc1p2x t36 vss v5 p_ad[13] r31 vss t37 dq[44] v6 vcc3p3 r32 vcc1p8 u1 p_ad[14] v7 vcc1p2 r33 ba[0] u2 p_cbe#[1] v8 vss r34 dq[32] u3 p_ad[15] v9 vcc1p2 r35 dq[37] u4 p_par v10 vss r36 dq[45] u5 vccvio v11 vcc1p2 r37 dq[40] u6 vccvio v12 vss t1 p_serr# u7 vss v13 vcc1p2 t2 vss u8 vcc1p2 v14 vss t3 p_stop# u9 vss v15 vcc1p2 t4 vss u10 vcc1p2 v16 vss table 14. intel? 81341 and 81342 i/o processors 1357-lead packagealphabetical ball listings (sheet 5 of 11) ball signal ball signal ball signal
intel ? 81341 and 81342 i/o processors december 2007 datasheet order number: 315039-003US 49 package informationintel ? 81341 and 81342 v17 vcc1p2 w23 vss y29 vcc3p3pllx v18 vss w24 vcc1p2x y30 vss v19 vcc1p2 w25 vss y31 vcc1p2x v20 vss w26 vcc1p2x y32 vcc1p8 v21 vcc1p2 w27 vss y33 ma[1] v22 vss w28 vcc1p2x y34 ma[2] v23 vcc1p2x w29 nc y35 vss v24 vss w30 vcc1p2x y36 cb[5] v25 vcc1p2x w31 vss y37 cb[1] v26 vss w32 vcc1p8 aa1 p_ad[3] v27 vcc1p2x w33 vss aa2 p_ad[1] v28 thermdc w34 m_ck[0] aa3 p_ad[2] v29 thermda w35 dm[8] aa4 p_ad[0] v30 vss w36 dqs[8] aa5 vccvio v31 vcc1p2x w37 dqs#[8] aa6 vccvio v32 vcc1p8 y1 p_ad[8] aa7 vss v33 ma[0] y2 p_ad[7] aa8 vcc1p2 v34 m_ck#[0] y3 p_ad[5] aa9 vss v35 vss y4 p_ad[6] aa10 vcc1p2 v36 cb[7] y5 p_ad[4] aa11 vss v37 cb[6] y6 vccvio aa12 vcc1p2 w1 vss y7 vcc1p2 aa13 vss w2 vss y8 vss aa14 vcc1p2 w3 p_cbe#[0] y9 vcc1p2 aa15 vss w4 vss y10 vss aa16 vcc1p2 w5 p_ad[9] y11 vcc1p2 aa17 vss w6 vcc3p3 y12 vss aa18 vcc1p2 w7 vss y13 vcc1p2 aa19 vss w8 vcc1p2 y14 vss aa20 vcc1p2 w9 vss y15 vcc1p2 aa21 vss w10 vcc1p2 y16 vss aa22 vcc1p2x w11 vss y17 vcc1p2 aa23 vss w12 vcc1p2 y18 vss aa24 vcc1p2x w13 vss y19 vcc1p2 aa25 vss w14 vcc1p2 y20 vss aa26 vcc1p2x w15 vss y21 vcc1p2 aa27 vss w16 vcc1p2 y22 vss aa28 vcc1p2x w17 vss y23 vcc1p2x aa29 vss w18 vcc1p2 y24 vss aa30 vcc1p2x w19 vss y25 vcc1p2x aa31 vss w20 vcc1p2 y26 vss aa32 vcc1p8 w21 vss y27 vcc1p2x aa33 ma[3] w22 vcc1p2x y28 vss aa34 m_ck#[1] table 14. intel? 81341 and 81342 i/o processors 1357-lead packagealphabetical ball listings (sheet 6 of 11) ball signal ball signal ball signal
intel ? 81341 and 81342package information intel ? 81341 and 81342 i/o processors datasheet december 2007 50 order number: 315039-003US aa35 m_ck[1] ac4 p_cbe#[5] ad10 vss aa36 cb[4] ac5 p_par64 ad11 vcc1p2 aa37 cb[0] ac6 vccvio ad12 vss ab1 p_ack64# ac7 vss ad13 vcc1p2 ab2 vss ac8 vcc1p2 ad14 vss ab3 p_req64# ac9 vss ad15 vcc1p2 ab4 vss ac10 vcc1p2 ad16 vss ab5 p_cbe#[7] ac11 vss ad17 vcc1p2 ab6 vcc3p3 ac12 vcc1p2 ad18 vss ab7 vcc1p2 ac13 vss ad19 vcc1p2 ab8 vss ac14 vcc1p2 ad20 vss ab9 vcc1p2 ac15 vss ad21 vcc1p2 ab10 vss ac16 vcc1p2 ad22 vss ab11 vcc1p2 ac17 vss ad23 vcc1p2x ab12 vss ac18 vcc1p2 ad24 vss ab13 vcc1p2 ac19 vss ad25 vcc1p2x ab14 vss ac20 vcc1p2 ad26 vss ab15 vcc1p2 ac21 vss ad27 vcc1p2x ab16 vss ac22 vcc1p2x ad28 vss ab17 vcc1p2 ac23 vss ad29 vcc1p2plld ab18 vss ac24 vcc1p2x ad30 vss ab19 vcc1p2 ac25 vss ad31 vcc1p2x ab20 vss ac26 vcc1p2x ad32 vcc1p8 ab21 vcc1p2 ac27 vss ad33 vss ab22 vss ac28 vcc1p2x ad34 dq[22] ab23 vcc1p2x ac29 vssplld ad35 dqs[2] ab24 vss ac30 vcc1p2x ad36 dq[30] ab25 vcc1p2x ac31 vss ad37 dqs[3] ab26 vss ac32 vcc1p8 ae1 p_ad[57] ab27 vcc1p2x ac33 ma[6] ae2 vss ab28 vss ac34 dq[23] ae3 p_ad[58] ab29 vcc1p2x ac35 dq[18] ae4 vss ab30 vss ac36 dq[26] ae5 p_ad[56] ab31 vcc1p2x ac37 dq[31] ae6 vcc3p3 ab32 vcc1p8 ad1 p_ad[61] ae7 vss ab33 ma[4] ad2 p_ad[59] ae8 vcc1p2 ab34 vss ad3 p_ad[62] ae9 vss ab35 dq[19] ad4 p_ad[60] ae10 vcc1p2 ab36 vss ad5 vccvio ae11 vss ab37 dq[27] ad6 vccvio ae12 vcc1p2 ac1 p_cbe#[6] ad7 vcc1p2 ae13 vss ac2 p_cbe#[4] ad8 vss ae14 vcc1p2 ac3 p_ad[63] ad9 vcc1p2 ae15 vss table 14. intel? 81341 and 81342 i/o processors 1357-lead packagealphabetical ball listings (sheet 7 of 11) ball signal ball signal ball signal
intel ? 81341 and 81342 i/o processors december 2007 datasheet order number: 315039-003US 51 package informationintel ? 81341 and 81342 ae16 vcc1p2 af22 vss ag28 vcc1p2x ae17 vss af23 vcc1p2x ag29 vss ae18 vcc1p2 af24 vss ag30 vcc1p2x ae19 vss af25 vcc1p2x ag31 vss ae20 vcc1p2 af26 vss ag32 vcc1p8 ae21 vss af27 vcc1p2x ag33 ma[7] ae22 vcc1p2x af28 vss ag34 dq[16] ae23 vss af29 vcc1p2x ag35 dq[21] ae24 vcc1p2x af30 vss ag36 dq[29] ae25 vss af31 vcc1p2x ag37 dq[24] ae26 vcc1p2x af32 vcc1p8 ah1 p_ad[45] ae27 vss af33 ma[8] ah2 vss ae28 vcc1p2x af34 dq[17] ah3 p_ad[46] ae29 vss af35 dm[2] ah4 vss ae30 vcc1p2x af36 dm[3] ah5 p_ad[44] ae31 vss af37 dq[25] ah6 vcc3p3 ae32 vcc1p8 ag1 p_ad[49] ah7 vcc1p2 ae33 ma[5] ag2 p_ad[47] ah8 vss ae34 vss ag3 p_ad[50] ah9 vcc1p2 ae35 dqs#[2] ag4 p_ad[48] ah10 vss ae36 vss ag5 vccvio ah11 vcc1p2 ae37 dqs#[3] ag6 vccvio ah12 vss af1 p_ad[55] ag7 vss ah13 vcc1p2 af2 p_ad[53] ag8 vcc1p2 ah14 vss af3 p_ad[51] ag9 vss ah15 vcc1p2 af4 p_ad[54] ag10 vcc1p2 ah16 vss af5 p_ad[52] ag11 vss ah17 vcc1p2 af6 vccvio ag12 vcc1p2 ah18 vss af7 vcc1p2 ag13 vss ah19 vcc1p2 af8 vss ag14 vcc1p2 ah20 vss af9 vcc1p2 ag15 vss ah21 vcc1p2 af10 vss ag16 vcc1p2 ah22 vss af11 vcc1p2 ag17 vss ah23 vcc1p2x af12 vss ag18 vcc1p2 ah24 vss af13 vcc1p2 ag19 vss ah25 vcc1p2x af14 vss ag20 vcc1p2 ah26 vss af15 vcc1p2 ag21 vss ah27 vcc1p2x af16 vss ag22 vcc1p2x ah28 vss af17 vcc1p2 ag23 vss ah29 vcc1p2x af18 vss ag24 vcc1p2x ah30 vss af19 vcc1p2 ag25 vss ah31 vcc1p2x af20 vss ag26 vcc1p2x ah32 vcc1p8 af21 vcc1p2 ag27 vss ah33 ma[9] table 14. intel? 81341 and 81342 i/o processors 1357-lead packagealphabetical ball listings (sheet 8 of 11) ball signal ball signal ball signal
intel ? 81341 and 81342package information intel ? 81341 and 81342 i/o processors datasheet december 2007 52 order number: 315039-003US ah34 vss ak3 p_ad[38] al9 vss ah35 dq[20] ak4 p_ad[36] al10 vcc1p2 ah36 vss ak5 vccvio al11 vss ah37 dq[28] ak6 vccvio al12 vcc1p2 aj1 p_ad[43] ak7 vcc1p2 al13 vss aj2 p_ad[41] ak8 vss al14 vcc1p2 aj3 p_ad[39] ak9 vcc1p2 al15 vss aj4 p_ad[42] ak10 vss al16 vcc1p2 aj5 p_ad[40] ak11 vcc1p2 al17 vss aj6 vccvio ak12 vss al18 vcc1p2 aj7 vss ak13 vcc1p2 al19 nc aj8 vcc1p2 ak14 vss al20 nc aj9 vss ak15 vcc1p2 al21 vss aj10 vcc1p2 ak16 vss al22 vcc1p2 aj11 vss ak17 vcc1p2 al23 vss aj12 vcc1p2 ak18 vss al24 vcc1p2x aj13 vss ak19 refclkn al25 vss aj14 vcc1p2 ak20 refclkp al26 vcc1p2x aj15 vss ak21 vcc1p2 al27 vcc1p2x aj16 vcc1p2 ak22 vss al28 vcc1p2x aj17 vss ak23 vcc1p2 al29 vss aj18 vcc1p2 ak24 vss al30 vcc1p2x aj19 vss ak25 vcc1p2x al31 vss aj20 vcc1p2 ak26 vss al32 vcc1p8 aj21 vss ak27 vcc1p2x al33 vss aj22 vcc1p2 ak28 vss al34 dq[6] aj23 vss ak29 vcc1p2x al35 dqs[0] aj24 vcc1p2x ak30 vss al36 dq[14] aj25 vss ak31 vcc1p2x al37 dqs[1] aj26 vcc1p2x ak32 vcc1p8 am1 a[24] aj27 vcc1p2x ak33 ma[12] am2 d[14] aj28 vcc1p2x ak34 dq[7] am3 pwe# aj29 vss ak35 dq[2] am4 poe# aj30 vcc1p2x ak36 dq[10] am5 d[10] aj31 vss ak37 dq[15] am6 vcc3p3 aj32 vcc1p8 al1 p_ad[33] am7 vcc3p3 aj33 ma[11] al2 vss am8 vcc3p3 aj34 vss al3 p_ad[34] am9 vcc3p3 aj35 dq[3] al4 vss am10 vcc3p3 aj36 vss al5 p_ad[32] am11 vcc3p3 aj37 dq[11] al6 vcc3p3 am12 vcc1p2 ak1 p_ad[37] al7 vss am13 vcc1p2e ak2 p_ad[35] al8 vcc1p2 am14 vcc1p2e table 14. intel? 81341 and 81342 i/o processors 1357-lead packagealphabetical ball listings (sheet 9 of 11) ball signal ball signal ball signal
intel ? 81341 and 81342 i/o processors december 2007 datasheet order number: 315039-003US 53 package informationintel ? 81341 and 81342 am15 vcc1p2ae an21 vcc1p8e ap27 vcc1p2x am16 vcc1p2ae an22 vcc1p8e ap28 vss am17 vcc1p2ae an23 vcc1p8e ap29 sda2 am18 vcc1p2ae an24 vcc1p8e ap30 vcc3p3 am19 nc an25 vcc1p8e ap31 vss am20 nc an26 vcc1p8e ap32 vcc1p8 am21 vcc1p2ae an27 vcc1p2x ap33 cke[1] am22 vcc1p2ae an28 scl2 ap34 dq[0] am23 vcc1p2ae an29 scl1 ap35 dq[5] am24 vcc1p2ae an30 vcc3p3 ap36 dq[13] am25 vcc1p8e an31 vcc3p3 ap37 dm[1] am26 vcc1p8e an32 vcc1p8 ar1 vss am27 vcc1p2x an33 cke[0] ar2 a[0] am28 vcc3p3 an34 dq[1] ar3 a[23] am29 vcc3p3 an35 dm[0] ar4 d[3] am30 vcc3p3 an36 dq[8] ar5 d[4] am31 vcc3p3 an37 dq[9] ar6 a[17] am32 vcc1p8 ap1 d[13] ar7 a[15] am33 ba[2] ap2 d[5] ar8 pb_rstout# am34 vss ap3 d[11] ar9 a[12] am35 dqs#[0] ap4 vss ar10 pce#[0] am36 vss ap5 d[9] ar11 a[19] am37 dqs#[1] ap6 a[16] ar12 vcc1p2 an1 d[7] ap7 vss ar13 vsse an2 d[6] ap8 a[10] ar14 petp[0] an3 d[12] ap9 a[9] ar15 petp[1] an4 d[2] ap10 vss ar16 vsse an5 vcc3p3 ap11 a[21] ar17 petp[2] an6 d[15] ap12 vcc1p2 ar18 petp[3] an7 a[11] ap13 vsse ar19 vsse an8 pur1 ap14 petn[0] ar20 petp[4] an9 nc ap15 petn[1] ar21 petp[5] an10 a[20] ap16 vsse ar22 vsse an11 pce#[1] ap17 petn[2] ar23 petp[6] an12 vcc1p2 ap18 petn[3] ar24 petp[7] an13 vcc1p2e ap19 vsse ar25 vsse an14 vcc1p2e ap20 petn[4] ar26 vcc1p8e an15 vcc1p2e ap21 petn[5] ar27 vcc1p2x an16 vcc1p2e ap22 vsse ar28 sda0 an17 vcc1p8e ap23 petn[6] ar29 sda1 an18 vcc1p8e ap24 petn[7] ar30 tdo an19 pe_caln ap25 vsse ar31 tck an20 pe_calp ap26 vcc1p8e ar32 vcc1p8 table 14. intel? 81341 and 81342 i/o processors 1357-lead packagealphabetical ball listings (sheet 10 of 11) ball signal ball signal ball signal
intel ? 81341 and 81342package information intel ? 81341 and 81342 i/o processors datasheet december 2007 54 order number: 315039-003US ar33 m_rst# at23 pern[6] au13 vsse ar34 vss at24 pern[7] au14 perp[0] ar35 dq[4] at25 vsse au15 perp[1] ar36 dq[12] at26 vcc1p8e au16 vsse ar37 vss at27 vcc1p2x au17 perp[2] at1 C at28 vss au18 perp[3] at2 vss at29 scl0 au19 vsse at3 d[0] at30 tms au20 perp[4] at4 d[8] at31 vss au21 perp[5] at5 a[4] at32 vcc1p8 au22 vsse at6 a[3] at33 m_vref au23 perp[6] at7 vss at34 m_cal[1] au24 perp[7] at8 a[1] at35 m_cal[0] au25 vsse at9 a[8] at36 vss au26 vcc1p8e at10 vss at37 C au27 vcc1p2x at11 a[18] au1 C au28 smbdat at12 vcc1p2 au2 C au29 smbclk at13 vsse au3 vss au30 tdi at14 pern[0] au4 d[1] au31 trst# at15 pern[1] au5 a[5] au32 vcc1p8 at16 vsse au6 a[7] au33 vss at17 pern[2] au7 a[2] au34 vss at18 pern[3] au8 a[6] au35 vss at19 vsse au9 a[14] au36 C at20 pern[4] au10 a[13] au37 C at21 pern[5] au11 a[22] at22 vsse au12 vcc1p2 a. ma[14] is only needed for 4gb memory support. when 4gb memory is not used this pin can be a nc. table 14. intel? 81341 and 81342 i/o processors 1357-lead packagealphabetical ball listings (sheet 11 of 11) ball signal ball signal ball signal
intel ? 81341 and 81342 i/o processors december 2007 datasheet order number: 315039-003US 55 package informationintel ? 81341 and 81342 table 15. intel? 81341 and 81342 i/o processors 1357-lead packagealphabetical signal listings (sheet 1 of 11) signal ball signal ball signal ball ? a1 cb[2] u37 dq[8] an36 ? a2 cb[3] u36 dq[9] an37 ? a36 cb[4] aa36 dq[10] ak36 ? a37 cb[5] y36 dq[11] aj37 ? b1 cb[6] v37 dq[12] ar36 ? b37 cb[7] v36 dq[13] ap36 ? at1 cke[0] an33 dq[14] al36 ? at37 cke[1] ap33 dq[15] ak37 ? au1 cs#[0] n33 dq[16] ag34 ? au2 cs#[1] g33 dq[17] af34 ? au36 d[0] at3 dq[18] ac35 ? au37 d[1] au4 dq[19] ab35 a[0] ar2 d[2] an4 dq[20] ah35 a[1] at8 d[3] ar4 dq[21] ag35 a[2] au7 d[4] ar5 dq[22] ad34 a[3] at6 d[5] ap2 dq[23] ac34 a[4] at5 d[6] an2 dq[24] ag37 a[5] au5 d[7] an1 dq[25] af37 a[6] au8 d[8] at4 dq[26] ac36 a[7] au6 d[9] ap5 dq[27] ab37 a[8] at9 d[10] am5 dq[28] ah37 a[9] ap9 d[11] ap3 dq[29] ag36 a[10] ap8 d[12] an3 dq[30] ad36 a[11] an7 d[13] ap1 dq[31] ac37 a[12] ar9 d[14] am2 dq[32] r34 a[13] au10 d[15] an6 dq[33] p34 a[14] au9 dm[0] an35 dq[34] l35 a[15] ar7 dm[1] ap37 dq[35] k35 a[16] ap6 dm[2] af35 dq[36] t35 a[17] ar6 dm[3] af36 dq[37] r35 a[18] at11 dm[4] p35 dq[38] m34 a[19] ar11 dm[5] p36 dq[39] l34 a[20] an10 dm[6] g35 dq[40] r37 a[21] ap11 dm[7] g36 dq[41] p37 a[22] au11 dm[8] w35 dq[42] l36 a[23] ar3 dq[0] ap34 dq[43] k37 a[24] am1 dq[1] an34 dq[44] t37 ba[0] r33 dq[2] ak35 dq[45] r36 ba[1] u33 dq[3] aj35 dq[46] m36 ba[2] am33 dq[4] ar35 dq[47] l37 cas# k33 dq[5] ap35 dq[48] h34 cb[0] aa37 dq[6] al34 dq[49] g34 cb[1] y37 dq[7] ak34 dq[50] d35
intel ? 81341 and 81342package information intel ? 81341 and 81342 i/o processors datasheet december 2007 56 order number: 315039-003US dq[51] c35 hs_led_out e8 nc a34 dq[52] j35 hs_lstat c6 nc b13 dq[53] h35 m_cal[0] at35 nc b14 dq[54] e34 m_cal[1] at34 nc b16 dq[55] d34 m_ck#[0] v34 nc b17 dq[56] h37 m_ck#[1] aa34 nc b19 dq[57] g37 m_ck#[2] u35 nc b20 dq[58] d36 m_ck[0] w34 nc b22 dq[59] c36 m_ck[1] aa35 nc b23 dq[60] j37 m_ck[2] u34 nc b25 dq[61] h36 m_rst# ar33 nc b26 dq[62] e36 m_vref at33 nc b28 dq[63] d37 ma[0] v33 nc b29 dqs#[0] am35 ma[1] y33 nc b31 dqs#[1] am37 ma[2] y34 nc b32 dqs#[2] ae35 ma[3] aa33 nc b33 dqs#[3] ae37 ma[4] ab33 nc b34 dqs#[4] n35 ma[5] ae33 nc b35 dqs#[5] n37 ma[6] ac33 nc c13 dqs#[6] f35 ma[7] ag33 nc c14 dqs#[7] f37 ma[8] af33 nc c16 dqs#[8] w37 ma[9] ah33 nc c17 dqs[0] al35 ma[10] t33 nc c19 dqs[1] al37 ma[11] aj33 nc c20 dqs[2] ad35 ma[12] ak33 nc c22 dqs[3] ad37 ma[13] h33 nc c23 dqs[4] m35 nc a13 nc c25 dqs[5] m37 nc a14 nc c26 dqs[6] e35 nc a16 nc c27 dqs[7] e37 nc a17 nc c28 dqs[8] w36 nc a19 nc c29 gpio[0] a10 nc a20 nc c30 gpio[1] a11 nc a22 nc c31 gpio[2] c10 nc a23 nc c32 gpio[3] b11 nc a25 ma[14] a c33 gpio[4] e10 nc a26 nc d5 gpio[5] d11 nc a27 nc d13 gpio[6] e11 nc a28 nc d14 gpio[7] c11 nc a29 nc d16 hpi# c7 nc a30 nc d17 hs_enum# a7 nc a31 nc d19 hs_freq[0] e6 nc a32 nc d20 hs_freq[1] d6 nc a33 nc d22 table 15. intel? 81341 and 81342 i/o processors 1357-lead packagealphabetical signal listings (sheet 2 of 11) signal ball signal ball signal ball
intel ? 81341 and 81342 i/o processors december 2007 datasheet order number: 315039-003US 57 package informationintel ? 81341 and 81342 nc d23 nc am19 p_ad[35] ak2 nc d25 nc am20 p_ad[36] ak4 nc d26 nc an9 p_ad[37] ak1 nc d28 nmi0# d8 p_ad[38] ak3 nc d29 nmi1# e7 p_ad[39] aj3 nc d31 odt[0] j33 p_ad[40] aj5 nc d32 odt[1] f33 p_ad[41] aj2 nc d33 p_ack64# ab1 p_ad[42] aj4 nc e3 p_ad[0] aa4 p_ad[43] aj1 nc e15 p_ad[1] aa2 p_ad[44] ah5 nc e16 p_ad[2] aa3 p_ad[45] ah1 nc e20 p_ad[3] aa1 p_ad[46] ah3 nc e21 p_ad[4] y5 p_ad[47] ag2 nc e25 p_ad[5] y3 p_ad[48] ag4 nc e26 p_ad[6] y4 p_ad[49] ag1 nc e27 p_ad[7] y2 p_ad[50] ag3 nc e28 p_ad[8] y1 p_ad[51] af3 nc e29 p_ad[9] w5 p_ad[52] af5 nc e30 p_ad[10] v2 p_ad[53] af2 nc e31 p_ad[11] v4 p_ad[54] af4 nc e32 p_ad[12] v3 p_ad[55] af1 nc f15 p_ad[13] v5 p_ad[56] ae5 nc f16 p_ad[14] u1 p_ad[57] ae1 nc f20 p_ad[15] u3 p_ad[58] ae3 nc f21 p_ad[16] r5 p_ad[59] ad2 nc f25 p_ad[17] n1 p_ad[60] ad4 nc f26 p_ad[18] p3 p_ad[61] ad1 nc f27 p_ad[19] m1 p_ad[62] ad3 nc f28 p_ad[20] p4 p_ad[63] ac3 nc f29 p_ad[21] m2 p_bmi f4 nc f30 p_ad[22] n3 p_cal[0] f5 nc f31 p_ad[23] m3 p_cal[1] f3 nc g1 p_ad[24] m4 p_cal[2] d3 nc g15 p_ad[25] l2 p_cbe#[0] w3 nc g16 p_ad[26] m5 p_cbe#[1] u2 nc g20 p_ad[27] k3 p_cbe#[2] p2 nc g21 p_ad[28] l3 p_cbe#[3] l1 nc h2 p_ad[29] k1 p_cbe#[4] ac2 nc j2 p_ad[30] l4 p_cbe#[5] ac4 nc j3 p_ad[31] k5 p_cbe#[6] ac1 nc w29 p_ad[32] al5 p_cbe#[7] ab5 nc al19 p_ad[33] al1 p_clkin d1 nc al20 p_ad[34] al3 p_clko[0] c2 table 15. intel? 81341 and 81342 i/o processors 1357-lead packagealphabetical signal listings (sheet 3 of 11) signal ball signal ball signal ball
intel ? 81341 and 81342package information intel ? 81341 and 81342 i/o processors datasheet december 2007 58 order number: 315039-003US p_clko[1] e1 perp[3] au18 u0_rxd b6 p_clko[2] c3 perp[4] au20 u0_txd b5 p_clko[3] b3 perp[5] au21 u1_cts# a4 p_clkout d2 perp[6] au23 u1_rts# c4 p_devsel# r3 perp[7] au24 u1_rxd c5 p_frame# r4 petn[0] ap14 u1_txd b4 p_gnt#[0] j5 petn[1] ap15 vcc1p2 e13 p_gnt#[1] j4 petn[2] ap17 vcc1p2 e17 p_gnt#[2] h3 petn[3] ap18 vcc1p2 e22 p_gnt#[3] g5 petn[4] ap20 vcc1p2 e23 p_idsel n5 petn[5] ap21 vcc1p2 e24 p_irdy# p1 petn[6] ap23 vcc1p2 f12 p_m66en v1 petn[7] ap24 vcc1p2 f14 p_par u4 petp[0] ar14 vcc1p2 f22 p_par64 ac5 petp[1] ar15 vcc1p2 f23 p_pcixcap r2 petp[2] ar17 vcc1p2 f24 p_perr# r1 petp[3] ar18 vcc1p2 g8 p_req#[0] j1 petp[4] ar20 vcc1p2 g10 p_req#[1] h1 petp[5] ar21 vcc1p2 g12 p_req#[2] g3 petp[6] ar23 vcc1p2 g13 p_req#[3] h4 petp[7] ar24 vcc1p2 g22 p_req64# ab3 poe# am4 vcc1p2 g23 p_rst# f2 pwe# am3 vcc1p2 g24 p_rstout# f1 ras# p33 vcc1p2 h7 p_serr# t1 refclkn ak19 vcc1p2 h9 p_stop# t3 refclkp ak20 vcc1p2 h11 p_trdy# t5 scl0 at29 vcc1p2 h13 pb_rstout# ar8 scl1 an29 vcc1p2 h17 pce#[0] ar10 scl2 an28 vcc1p2 h19 pce#[1] an11 sda0 ar28 vcc1p2 h23 pe_caln an19 sda1 ar29 vcc1p2 j8 pe_calp an20 sda2 ap29 vcc1p2 j10 pern[0] at14 smbclk au29 vcc1p2 j12 pern[1] at15 smbdat au28 vcc1p2 j14 pern[2] at17 tck ar31 vcc1p2 j15 pern[3] at18 tdi au30 vcc1p2 j18 pern[4] at20 tdo ar30 vcc1p2 j20 pern[5] at21 thermda v29 vcc1p2 j22 pern[6] at23 thermdc v28 vcc1p2 j24 pern[7] at24 tms at30 vcc1p2 k7 perp[0] au14 trst# au31 vcc1p2 k9 perp[1] au15 u0_cts# a5 vcc1p2 k11 perp[2] au17 u0_rts# a6 vcc1p2 k13 table 15. intel? 81341 and 81342 i/o processors 1357-lead packagealphabetical signal listings (sheet 4 of 11) signal ball signal ball signal ball
intel ? 81341 and 81342 i/o processors december 2007 datasheet order number: 315039-003US 59 package informationintel ? 81341 and 81342 vcc1p2 k15 vcc1p2 t13 vcc1p2 ab9 vcc1p2 k17 vcc1p2 t15 vcc1p2 ab11 vcc1p2 k19 vcc1p2 t17 vcc1p2 ab13 vcc1p2 k21 vcc1p2 t19 vcc1p2 ab15 vcc1p2 l8 vcc1p2 t21 vcc1p2 ab17 vcc1p2 l10 vcc1p2 u8 vcc1p2 ab19 vcc1p2 l12 vcc1p2 u10 vcc1p2 ab21 vcc1p2 l14 vcc1p2 u12 vcc1p2 ac8 vcc1p2 l16 vcc1p2 u14 vcc1p2 ac10 vcc1p2 l18 vcc1p2 u16 vcc1p2 ac12 vcc1p2 l20 vcc1p2 u18 vcc1p2 ac14 vcc1p2 m7 vcc1p2 u20 vcc1p2 ac16 vcc1p2 m9 vcc1p2 v7 vcc1p2 ac18 vcc1p2 m11 vcc1p2 v9 vcc1p2 ac20 vcc1p2 m13 vcc1p2 v11 vcc1p2 ad7 vcc1p2 m15 vcc1p2 v13 vcc1p2 ad9 vcc1p2 m17 vcc1p2 v15 vcc1p2 ad11 vcc1p2 m19 vcc1p2 v17 vcc1p2 ad13 vcc1p2 m21 vcc1p2 v19 vcc1p2 ad15 vcc1p2 n8 vcc1p2 v21 vcc1p2 ad17 vcc1p2 n10 vcc1p2 w8 vcc1p2 ad19 vcc1p2 n12 vcc1p2 w10 vcc1p2 ad21 vcc1p2 n14 vcc1p2 w12 vcc1p2 ae8 vcc1p2 n16 vcc1p2 w14 vcc1p2 ae10 vcc1p2 n18 vcc1p2 w16 vcc1p2 ae12 vcc1p2 n20 vcc1p2 w18 vcc1p2 ae14 vcc1p2 p7 vcc1p2 w20 vcc1p2 ae16 vcc1p2 p9 vcc1p2 y7 vcc1p2 ae18 vcc1p2 p13 vcc1p2 y9 vcc1p2 ae20 vcc1p2 p15 vcc1p2 y11 vcc1p2 af7 vcc1p2 p17 vcc1p2 y13 vcc1p2 af9 vcc1p2 p19 vcc1p2 y15 vcc1p2 af11 vcc1p2 p21 vcc1p2 y17 vcc1p2 af13 vcc1p2 r8 vcc1p2 y19 vcc1p2 af15 vcc1p2 r10 vcc1p2 y21 vcc1p2 af17 vcc1p2 r12 vcc1p2 aa8 vcc1p2 af19 vcc1p2 r14 vcc1p2 aa10 vcc1p2 af21 vcc1p2 r16 vcc1p2 aa12 vcc1p2 ag8 vcc1p2 r18 vcc1p2 aa14 vcc1p2 ag10 vcc1p2 r20 vcc1p2 aa16 vcc1p2 ag12 vcc1p2 t7 vcc1p2 aa18 vcc1p2 ag14 vcc1p2 t9 vcc1p2 aa20 vcc1p2 ag16 vcc1p2 t11 vcc1p2 ab7 vcc1p2 ag18 table 15. intel? 81341 and 81342 i/o processors 1357-lead packagealphabetical signal listings (sheet 5 of 11) signal ball signal ball signal ball
intel ? 81341 and 81342package information intel ? 81341 and 81342 i/o processors datasheet december 2007 60 order number: 315039-003US vcc1p2 ag20 vcc1p2ae am22 vcc1p2x r22 vcc1p2 ah7 vcc1p2ae am23 vcc1p2x r24 vcc1p2 ah9 vcc1p2ae am24 vcc1p2x r26 vcc1p2 ah11 vcc1p2e am13 vcc1p2x r28 vcc1p2 ah13 vcc1p2e am14 vcc1p2x r30 vcc1p2 ah15 vcc1p2e an13 vcc1p2x t23 vcc1p2 ah17 vcc1p2e an14 vcc1p2x t25 vcc1p2 ah19 vcc1p2e an15 vcc1p2x t27 vcc1p2 ah21 vcc1p2e an16 vcc1p2x t29 vcc1p2 aj8 vcc1p2plld ad29 vcc1p2x t31 vcc1p2 aj10 vcc1p2pllp p11 vcc1p2x u22 vcc1p2 aj12 vcc1p2x h25 vcc1p2x u24 vcc1p2 aj14 vcc1p2x h27 vcc1p2x u26 vcc1p2 aj16 vcc1p2x h29 vcc1p2x u28 vcc1p2 aj18 vcc1p2x h31 vcc1p2x u30 vcc1p2 aj20 vcc1p2x j26 vcc1p2x v23 vcc1p2 aj22 vcc1p2x j28 vcc1p2x v25 vcc1p2 ak7 vcc1p2x j30 vcc1p2x v27 vcc1p2 ak9 vcc1p2x k23 vcc1p2x v31 vcc1p2 ak11 vcc1p2x k25 vcc1p2x w22 vcc1p2 ak13 vcc1p2x k27 vcc1p2x w24 vcc1p2 ak15 vcc1p2x k29 vcc1p2x w26 vcc1p2 ak17 vcc1p2x k31 vcc1p2x w28 vcc1p2 ak21 vcc1p2x l22 vcc1p2x w30 vcc1p2 ak23 vcc1p2x l24 vcc1p2x y23 vcc1p2 al8 vcc1p2x l26 vcc1p2x y25 vcc1p2 al10 vcc1p2x l28 vcc1p2x y27 vcc1p2 al12 vcc1p2x l30 vcc1p2x y31 vcc1p2 al14 vcc1p2x m23 vcc1p2x aa22 vcc1p2 al16 vcc1p2x m25 vcc1p2x aa24 vcc1p2 al18 vcc1p2x m27 vcc1p2x aa26 vcc1p2 al22 vcc1p2x m29 vcc1p2x aa28 vcc1p2 am12 vcc1p2x m31 vcc1p2x aa30 vcc1p2 an12 vcc1p2x n22 vcc1p2x ab23 vcc1p2 ap12 vcc1p2x n24 vcc1p2x ab25 vcc1p2 ar12 vcc1p2x n26 vcc1p2x ab27 vcc1p2 at12 vcc1p2x n28 vcc1p2x ab29 vcc1p2 au12 vcc1p2x n30 vcc1p2x ab31 vcc1p2ae am15 vcc1p2x p23 vcc1p2x ac22 vcc1p2ae am16 vcc1p2x p25 vcc1p2x ac24 vcc1p2ae am17 vcc1p2x p27 vcc1p2x ac26 vcc1p2ae am18 vcc1p2x p29 vcc1p2x ac28 vcc1p2ae am21 vcc1p2x p31 vcc1p2x ac30 table 15. intel? 81341 and 81342 i/o processors 1357-lead packagealphabetical signal listings (sheet 6 of 11) signal ball signal ball signal ball
intel ? 81341 and 81342 i/o processors december 2007 datasheet order number: 315039-003US 61 package informationintel ? 81341 and 81342 vcc1p2x ad23 vcc1p2x au27 vcc1p8e an23 vcc1p2x ad25 vcc1p8 e18 vcc1p8e an24 vcc1p2x ad27 vcc1p8 e19 vcc1p8e an25 vcc1p2x ad31 vcc1p8 f18 vcc1p8e an26 vcc1p2x ae22 vcc1p8 f19 vcc1p8e ap26 vcc1p2x ae24 vcc1p8 g18 vcc1p8e ar26 vcc1p2x ae26 vcc1p8 g19 vcc1p8e at26 vcc1p2x ae28 vcc1p8 h32 vcc1p8e au26 vcc1p2x ae30 vcc1p8 j32 vcc3p3 e5 vcc1p2x af23 vcc1p8 k32 vcc3p3 f6 vcc1p2x af25 vcc1p8 l32 vcc3p3 f7 vcc1p2x af27 vcc1p8 m32 vcc3p3 f8 vcc1p2x af29 vcc1p8 n32 vcc3p3 f9 vcc1p2x af31 vcc1p8 p32 vcc3p3 f10 vcc1p2x ag22 vcc1p8 r32 vcc3p3 f11 vcc1p2x ag24 vcc1p8 t32 vcc3p3 f32 vcc1p2x ag26 vcc1p8 u32 vcc3p3 g6 vcc1p2x ag28 vcc1p8 v32 vcc3p3 g25 vcc1p2x ag30 vcc1p8 w32 vcc3p3 g26 vcc1p2x ah23 vcc1p8 y32 vcc3p3 g27 vcc1p2x ah25 vcc1p8 aa32 vcc3p3 g28 vcc1p2x ah27 vcc1p8 ab32 vcc3p3 g29 vcc1p2x ah29 vcc1p8 ac32 vcc3p3 g30 vcc1p2x ah31 vcc1p8 ad32 vcc3p3 g31 vcc1p2x aj24 vcc1p8 ae32 vcc3p3 g32 vcc1p2x aj26 vcc1p8 af32 vcc3p3 j6 vcc1p2x aj27 vcc1p8 ag32 vcc3p3 k6 vcc1p2x aj28 vcc1p8 ah32 vcc3p3 n6 vcc1p2x aj30 vcc1p8 aj32 vcc3p3 r6 vcc1p2x ak25 vcc1p8 ak32 vcc3p3 t6 vcc1p2x ak27 vcc1p8 al32 vcc3p3 v6 vcc1p2x ak29 vcc1p8 am32 vcc3p3 w6 vcc1p2x ak31 vcc1p8 an32 vcc3p3 ab6 vcc1p2x al24 vcc1p8 ap32 vcc3p3 ae6 vcc1p2x al26 vcc1p8 ar32 vcc3p3 ah6 vcc1p2x al27 vcc1p8 at32 vcc3p3 al6 vcc1p2x al28 vcc1p8 au32 vcc3p3 am6 vcc1p2x al30 vcc1p8e am25 vcc3p3 am7 vcc1p2x am27 vcc1p8e am26 vcc3p3 am8 vcc1p2x an27 vcc1p8e an17 vcc3p3 am9 vcc1p2x ap27 vcc1p8e an18 vcc3p3 am10 vcc1p2x ar27 vcc1p8e an21 vcc3p3 am11 vcc1p2x at27 vcc1p8e an22 vcc3p3 am28 table 15. intel? 81341 and 81342 i/o processors 1357-lead packagealphabetical signal listings (sheet 7 of 11) signal ball signal ball signal ball
intel ? 81341 and 81342package information intel ? 81341 and 81342 i/o processors datasheet december 2007 62 order number: 315039-003US vcc3p3 am29 vss b21 vss h16 vcc3p3 am30 vss b24 vss h18 vcc3p3 am31 vss b27 vss h20 vcc3p3 an5 vss b30 vss h21 pur1 an8 vss b36 vss h22 vcc3p3 an30 vss c1 vss h24 vcc3p3 an31 vss c12 vss h26 vcc3p3 ap30 vss c15 vss h28 vcc3p3pllx y29 vss c18 vss h30 vccvio h5 vss c21 vss j7 vccvio h6 vss c24 vss j9 vccvio l5 vss c34 vss j11 vccvio l6 vss c37 vss j13 vccvio m6 vss d4 vss j16 vccvio p5 vss d7 vss j17 vccvio p6 vss d10 vss j19 vccvio u5 vss d12 vss j21 vccvio u6 vss d15 vss j23 vccvio y6 vss d18 vss j25 vccvio aa5 vss d21 vss j27 vccvio aa6 vss d24 vss j29 vccvio ac6 vss d27 vss j31 vccvio ad5 vss d30 vss j34 vccvio ad6 vss e2 vss j36 vccvio af6 vss e12 vss k2 vccvio ag5 vss e14 vss k4 vccvio ag6 vss e33 vss k8 vccvio aj6 vss f13 vss k10 vccvio ak5 vss f17 vss k12 vccvio ak6 vss f34 vss k14 vss a3 vss f36 vss k16 vss a12 vss g2 vss k18 vss a15 vss g4 vss k20 vss a18 vss g7 vss k22 vss a21 vss g9 vss k24 vss a24 vss g11 vss k26 vss a35 vss g14 vss k28 vss b2 vss g17 vss k30 vss b7 vss h8 vss k34 vss b10 vss h10 vss k36 vss b12 vss h12 vss l7 vss b15 vss h14 vss l9 vss b18 vss h15 vss l11 table 15. intel? 81341 and 81342 i/o processors 1357-lead packagealphabetical signal listings (sheet 8 of 11) signal ball signal ball signal ball
intel ? 81341 and 81342 i/o processors december 2007 datasheet order number: 315039-003US 63 package informationintel ? 81341 and 81342 vss l13 vss p16 vss u19 vss l15 vss p18 vss u21 vss l17 vss p20 vss u23 vss l19 vss p22 vss u25 vss l21 vss p24 vss u27 vss l23 vss p26 vss u31 vss l25 vss p28 vss v8 vss l27 vss p30 vss v10 vss l29 vss r7 vss v12 vss l31 vss r9 vss v14 vss m8 vss r11 vss v16 vss m10 vss r13 vss v18 vss m12 vss r15 vss v20 vss m14 vss r17 vss v22 vss m16 vss r19 vss v24 vss m18 vss r21 vss v26 vss m20 vss r23 vss v30 vss m22 vss r25 vss v35 vss m24 vss r27 vss w1 vss m26 vss r29 vss w2 vss m28 vss r31 vss w4 vss m30 vss t2 vss w7 vss m33 vss t4 vss w9 vss n2 vss t8 vss w11 vss n4 vss t10 vss w13 vss n7 vss t12 vss w15 vss n9 vss t14 vss w17 vss n13 vss t16 vss w19 vss n15 vss t18 vss w21 vss n17 vss t20 vss w23 vss n19 vss t22 vss w25 vss n21 vss t24 vss w27 vss n23 vss t26 vss w31 vss n25 vss t28 vss w33 vss n27 vss t30 vss y8 vss n29 vss t34 vss y10 vss n31 vss t36 vss y12 vss n34 vss u7 vss y14 vss n36 vss u9 vss y16 vss p8 vss u11 vss y18 vss p10 vss u13 vss y20 vss p12 vss u15 vss y22 vss p14 vss u17 vss y24 table 15. intel? 81341 and 81342 i/o processors 1357-lead packagealphabetical signal listings (sheet 9 of 11) signal ball signal ball signal ball
intel ? 81341 and 81342package information intel ? 81341 and 81342 i/o processors datasheet december 2007 64 order number: 315039-003US vss y26 vss ac27 vss af30 vss y28 vss ac31 vss ag7 vss y30 vss ad8 vss ag9 vss y35 vss ad10 vss ag11 vss aa7 vss ad12 vss ag13 vss aa9 vss ad14 vss ag15 vss aa11 vss ad16 vss ag17 vss aa13 vss ad18 vss ag19 vss aa15 vss ad20 vss ag21 vss aa17 vss ad22 vss ag23 vss aa19 vss ad24 vss ag25 vss aa21 vss ad26 vss ag27 vss aa23 vss ad28 vss ag29 vss aa25 vss ad30 vss ag31 vss aa27 vss ad33 vss ah2 vss aa29 vss ae2 vss ah4 vss aa31 vss ae4 vss ah8 vss ab2 vss ae7 vss ah10 vss ab4 vss ae9 vss ah12 vss ab8 vss ae11 vss ah14 vss ab10 vss ae13 vss ah16 vss ab12 vss ae15 vss ah18 vss ab14 vss ae17 vss ah20 vss ab16 vss ae19 vss ah22 vss ab18 vss ae21 vss ah24 vss ab20 vss ae23 vss ah26 vss ab22 vss ae25 vss ah28 vss ab24 vss ae27 vss ah30 vss ab26 vss ae29 vss ah34 vss ab28 vss ae31 vss ah36 vss ab30 vss ae34 vss aj7 vss ab34 vss ae36 vss aj9 vss ab36 vss af8 vss aj11 vss ac7 vss af10 vss aj13 vss ac9 vss af12 vss aj15 vss ac11 vss af14 vss aj17 vss ac13 vss af16 vss aj19 vss ac15 vss af18 vss aj21 vss ac17 vss af20 vss aj23 vss ac19 vss af22 vss aj25 vss ac21 vss af24 vss aj29 vss ac23 vss af26 vss aj31 vss ac25 vss af28 vss aj34 table 15. intel? 81341 and 81342 i/o processors 1357-lead packagealphabetical signal listings (sheet 10 of 11) signal ball signal ball signal ball
intel ? 81341 and 81342 i/o processors december 2007 datasheet order number: 315039-003US 65 package informationintel ? 81341 and 81342 vss aj36 vss am36 vsse ar22 vss ak8 vss ap4 vsse ar25 vss ak10 vss ap7 vsse at13 vss ak12 vss ap10 vsse at16 vss ak14 vss ap28 vsse at19 vss ak16 vss ap31 vsse at22 vss ak18 vss ar1 vsse at25 vss ak22 vss ar34 vsse au13 vss ak24 vss ar37 vsse au16 vss ak26 vss at2 vsse au19 vss ak28 vss at7 vsse au22 vss ak30 vss at10 vsse au25 vss al2 vss at28 vssplld ac29 vss al4 vss at31 vsspllp n11 vss al7 vss at36 vsspllx u29 vss al9 vss au3 warm_rst# e4 vss al11 vss au33 we# l33 vss al13 vss au34 xint#[0] b8 vss al15 vss au35 xint#[1] a9 vss al17 vsse ap13 xint#[2] a8 vss al21 vsse ap16 xint#[3] b9 vss al23 vsse ap19 xint#[4] d9 vss al25 vsse ap22 xint#[5] c9 vss al29 vsse ap25 xint#[6] c8 vss al31 vsse ar13 xint#[7] e9 vss al33 vsse ar16 vss am34 vsse ar19 a. ma[14] is only needed for 4gb memory support. when 4gb memory is not used this pin can be a nc. table 15. intel? 81341 and 81342 i/o processors 1357-lead packagealphabetical signal listings (sheet 11 of 11) signal ball signal ball signal ball
intel ? 81341 and 81342electrical specifications intel ? 81341 and 81342 i/o processors datasheet december 2007 66 order number: 315039-003US 4.0 electrical specifications table 16. absolute maximum ratings parameter maximum rating notice: this data sheet contains informa- tion on products in the design phase of development. do not finalize a design with this informa- tion. revised information will be published when the product becomes available. the specifica- tions are subject to change without notice. contact your local intel rep- resentative before finalizing a design. storage temperature C10 c to +45 c supply voltage v cc3p3 wrt. v ss C0.5 v to +4.1 v supply voltage v cc1p8e wrt. v sse C0.5 v to +2.5 v supply voltage v cc1p8 wrt. v ss C0.5 v to +2.5 v supply voltage v ccvio wrt. v ss C0.5 v to +4.1 v supply voltage v cc1p2x wrt. v ss C0.5 v to +1.8 v supply voltage v cc1p2 wrt. v ss C0.5 v to +1.8 v supply voltage v cc1p2ae wrt. v sse C0.5 v to +1.8 v supply voltage v cc1p2e wrt. v sse C0.5 v to +1.8 v voltage on any ball wrt. v ss C0.5 v to v ccp +0.5 v ? warning: stressing the device beyond the absolute maximum ratings may cause permanent damage. these are stress ratings only. operation beyond the operating conditions is not recommended and extended exposure beyond the operating conditions may affect device reliability.
intel ? 81341 and 81342 i/o processors december 2007 datasheet order number: 315039-003US 67 electrical specificationsintel ? 81341 and 81342 table 17. operating conditions symbol parameter minimum maximum units notes v cc3p3 3.3 v supply voltage for pci-x category 2 signals and general purpose i/os 3.0 3.6 v v cc1p8e 1.8 v supply voltage for pci express* interface 1.71 1.89 v v cc1p8 1.8 v supply voltage for ddr2 sdram memory interface i/os 1.71 1.89 v v ccvio 3.3 v supply voltage for pci-x category 1 signals 3.0 3.6 v v cc1p2x 1.2 v supply voltage for intel xscale ? processors 1.164 1.236 v v cc1p2 1.2 v supply voltage for most digital logic 1.164 1.236 v v cc1p2e 1.2 v supply voltage for pci express* interface digital logic 1.164 1.236 v v cc1p2ae 1.2 v supply voltage for pci express* interface analog logic 1.164 1.236 v v cc1p2pllp 1.2 v supply voltage for pci-x pll 1.164 1.236 v v cc1p2plld 1.2 v supply voltage for ddr2 sdram pll processor logic pll. 1.164 1.236 v v cc3p3pllx 3.3 v supply voltage for processor logic pll 3.0 3.6 v m_vref memory i/o reference voltage 0.49 v cc1p8 0.51 v cc1p8 v t c case temperature under bias 0100c
intel ? 81341 and 81342electrical specifications intel ? 81341 and 81342 i/o processors datasheet december 2007 68 order number: 315039-003US 4.1 v ccpll pin requirements to reduce clock jitter, the v cc1p2plld , v cc1p2pllp , and v cc3p3pllx balls for the phase-lock loop (pll) circuits are isolated on the package. the low-pass filters, as shown in the following figures, reduce noise-induced clock jitter and its effects on timing relationships in system design. this paragraph pertains to the v cc1p2plld , v cc1p2pllp , v cc3p3pllx filters. the filter components must be able to handle a dc current of 30 ma. use a shielded type inductor to minimize magnetic pickup. the total series resistance from the board vcc plane (before the filter) to the vccpll ball must be less than 1.5 ohm (including component and trace resistance). the total series resistance from the board vcc plane (before the filter) to the top plate of the capacitor must be greater than 0.35 ohm (including component and trace resistance). the nodes connecting vccpll and vsspll to the capacitor must be as short as possible (less than 0.1 w). vccpll and vsspll must be routed close to each other to minimize loop area. the vsspll balls must be connected to the filter only and not to any other ground, as shown in figure 8 and figure 9 . the inductor and capacitor must be placed close to each other. any discrete resistor must be placed between the vcc board plane and the inductor. if the trace and component resistance is high enough, a discrete resistor might not be required. the bypass capacitor must be placed as close to the supply pins as possible. the series impedances to both the supply pin and the pcb analog ground plane must be an order of magnitude lower than the esr and esl specified for the capacitor. figure 8. v cc3p3pllx low-pass filter figure 9. v cc1p2plld , v cc1p2pllp low-pass filter 3.3v (board plane) 22 f 20%, esr < 0.3, 4.7 uh, 25% v sspllx 6.3 v, esl < 2.5nh (not connected to board ground) v cc3p3pllx (board plane) 22 f, 20%, esr < 0.3, 4.7 uh, 25% 1.2v 6.3 v, esl < 2.5nh (not connected to board ground) v ssplld / v sspllp v cc1p2plld / v cc1p2pllp
intel ? 81341 and 81342 i/o processors december 2007 datasheet order number: 315039-003US 69 electrical specificationsintel ? 81341 and 81342 4.2 targeted dc specifications table 18. dc characteristics symbol parameter minimum maximum unit s notes v il1 input low voltage (general purpose). -0.3 0.3 v cc3p3 v 2 v ih1 input high voltage (general purpose). 2.0 v cc3p3 + 0.3 v 2 v il2 input low voltage (pci). -0.5 0.3 v cc3p3 v v il3 input low voltage (pci-x). -0.5 0.35 v cc3p3 v v ih3 input high voltage (pci-x/pci). 0.5 v cc3p3 v cc3p3 + 0.5 v v il4 input low voltage (ddr2 sdram). -0.3 m_vref - 0.125 v v ih4 input high voltage (ddr2 sdram). m_vref + 0.125 v cc1p8 + 0.3 v v ol1 output low voltage (general purpose). ? 0.4 v i ol = 10 ma 2 v oh1 output high voltage (general purpose). 2.6 ? v i oh = -10 ma 2 v ol2 output low voltage (pci-x). ? 0.1 v cc3p3 v i ol = 1.50 ma v oh2 output high voltage (pci-x). 0.9 v cc3p3 ?v i oh = -0.50 ma v ol3 output low voltage (ddr2 sdram driver set to 21 ? ). 0.28 v i ol = 11 ma v oh3 output high voltage (ddr2 sdram driver set to 21 ? ). 1.42 v i oh = -11 ma v ol4 output low voltage (ddr2 sdram driver set to 50 ? ). 0.28 v i ol = 5 ma v oh4 output high voltage (ddr2 sdram driver set to 50 ? ). 1.42 v i oh = -5 ma i li1 input leakage current for general purpose pins when internal pull up resistors are not enabled. 5 a 0 v in v cc3p3 3 i li2 input leakage current for pci-x pins when internal pull up resistors are not enabled. 10 a 0 v in v cc3p3 (cat . 2) 0 v in v ccvio (cat. 1) 3 i li3 input leakage current for ddr2 pins when internal pull up resistors are not enabled. 2 a 0 v in v cc1p8 3 r gp internal pull up resistor value for general purpose pins. 28.5 38.7 ? 1 r pcix internal pull up resistor value for pci-x pins. 5.9 8.1 ? 1 c gp general purpose pin capacitance. 1 4.5 pf 1 c pcix pci-x pin capacitance. 1 4.5 pf 1 c ddr2 ddr2 pin capacitance. 1 4.5 pf 1 l pin ball inductance. 112nh 1 notes: 1. not tested, guaranteed by design. 2. general purpose signals include all signals that are not part of the ddr2, pci-x and pci-express interfaces and analog pins. 3. input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs.
intel ? 81341 and 81342electrical specifications intel ? 81341 and 81342 i/o processors datasheet december 2007 70 order number: 315039-003US table 19. i cc characteristics symbol parameter typ max units notes icc12 active two cores (81342) (power supply) power supply current: ? pci express a&d ? intel xscale ? michroarchitectures - 800mhz - 1200mhz 6.93 7.69 a1, 2, 4 icc12 active single core (81341) (power supply) power supply current: ? pci express a&d ? intel xscale ? michroarchitectures - 800mhz - 1200mhz 6.53 7.28 a1, 2, 4 icc18 active (power supply) power supply current: ? pci express i/os ? ddr-ii (533) 1.52 a1, 2, 4 icc33 active (power supply) power supply current: ? pci, pbi, gpio ? pci-x i/os 0.69 a1, 2 icc12 active two cores (81342) (thermal) thermal current: ? pci express a&d ? intel xscale ? michroarchitecture: 800mhz 1200mhz 4.82 6.00 a1, 3, 4 icc12 active single core (81341) (thermal) thermal current: ? pci express a&d ? intel xscale ? michroarchitecture: 800mhz 1200mhz 4.48 5.62 a1, 3, 4 icc18 active (thermal) thermal current: ? pci express i/os ? ddr-ii (533) 1.31 a1, 3, 4 icc33 active (thermal) thermal current:: ? pci, pbi, gpio ? pci-x i/os 0.58 a1, 3 notes: 1. measured with the device operating and outputs loaded to the test condition in figure 17, ac test load for all signals except pci, pci-express and ddr2 on page 85 . 2. icc active (power supply) value is provided for selecting the system power supply. this is based on the worst case data patterns and skew material at the following worst case voltages: vcc33 = 3.63 v, vcc18 = 1.89 v, vcc12 = 1.24 v and ambient temperature = 55c. 3. icc active (thermal) value is provided for selecting the system thermal design power (tdp). this is based on the following typical voltages: vcc33 = 3.3 v, vcc18 = 1.8 v, vcc12 = 1.2 v and ambient temperature = 55c. 4. the customer reference boards use a 1.2 v switching regulator for all the 1.2 v supplies (vcc1p2, vcc1p2x, vcc1p2e, vcc1p2ae) and a 1.8 v switching regulator for all 1.8 v supplies: (vcc1p8, vcc1p8e).
intel ? 81341 and 81342 i/o processors december 2007 datasheet order number: 315039-003US 71 electrical specificationsintel ? 81341 and 81342 4.3 targeted ac specifications 4.3.1 clock signal timings table 20. pci clock timings symbol parameter pci-x 133 pci-x 100 pci-x 66 pci 66 pci 33 units notes min. max min. max min. max min. max min. max t c1 pci clock cycle time jitter class 1 7.5 11 10 15 152215253050 ns 1 t c2 pci clock cycle time jitter class 2 7.375 11 9.875 15 14.8 22 14.8 25 29.7 50 1 t ch1 pci clock high time 2.5 3 5.5 5.5 10 ns tcl1 pci clock low time 2.5 3 5.5 5.5 10 ns pci clock period jitter 125 -125 125 -125 200 -200 200 -200 300 -300 ps 3 tsr1 pci clock slew rate 1.5 4 1.5 4 1.5 4 1.5 4 1 4 v/ns 2 pci spread spectrum requirements f mod pci clock modulation frequency 30 33 30 33 30 33 30 33 khz f spread pci clock frequency spread -10-10-10-10 % pci output clocks pci output clock skew 250 350 350 350 350 ps pci output clock period jitter 100 -100 150 -150 150 -150 150 -150 150 -150 ps 4, 5 notes: 1. the clock frequency may not change beyond the spread-spectrum limits except while p_rst# or warm_rst# is asserted. 2. this slew rate must be met across the minimum peak-to-peak portion of the clock waveform. 3. period jitter is the deviation between any single period of the clock and the average period of the clock. 4. if a jitter class 2 input clock is used, output clocks can not support jitter class 1. 5. the deviation between any single period of the clock and the average period of the clock.
intel ? 81341 and 81342electrical specifications intel ? 81341 and 81342 i/o processors datasheet december 2007 72 order number: 315039-003US table 21. pci express* clock timings symbol parameter min. nom. max. units notes tf2 pci express* clock frequency 100 mhz 4 tc2 pci express* clock cycle time 9.872 ns df0 frequency variation -300 300 ppm tccj cycle to cycle jitter 125 ps tppj peak to peak jitter (5C50 mhz) 50 ps dc clock duty cycle 45 55 % trise refclk rise time 175 350 ps 1 , 2 , 7 tfall refclk fall time 175 350 ps 1 , 2 , 7 tvrise refclk rise time variation 125 ps tvfall refclk fall time variation 125 ps rise-fall matching 20 % vca absolute cross point 0.25 0.55 v 1 , 3 , 8 , 14 vcr relative cross point calc calc 5 , 13 tvc total variation of vc over all edges 0.14 v 14 rising edge ringback 0.56 v absolute min. falling edge ringback 0.25 v absolute max. vhi high level voltage 0.66 0.71 0.85 v 8 , 9 vli low level voltage -0.15 0 0.15 v 8 , 10 vrb ringback voltage 0.10 v 8 vovs maximum overshoot vhi+0.3 v 8 , 11 vuds minimum undershoot -0.30 v 8 , 12 notes: 1. measured at crossing point where the instantaneous voltage value of the rising edge of refclk equals the falling edge of refclk#. 2. measured from v ol =0.175v to v oh = 0.525 v. valid only for rising refclk and falling refclk#. signal must be monotonic through the v ol to v oh region for t rise and t fall . 3. this measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. 4. the average period over any 1 s period of time must be greater than the minimum specified period. 5. v cross (rel) min and max are derived using the following: v cross (rel) min = 0.5 (v havg - 0.710) + 0.250 v cross (rel) max = 0.5 (v havg - 0.710) + 0.550 6. (see for further clarification). 7. measurement taken from single-ended waveform. 8. measurement taken from differential waveform. 9. v high is defined as the statistical average high value as obtained by using the oscilloscope v high math function. 10. v low is defined as the statistical average low value as obtained by using the osc illoscope v low math function. 11. overshoot is defined as the absolute value of the maximum voltage. 12. undershoot is defined as the absolute value of the minimum voltage. 13. the crossing point must meet the absolute and relative crossing point specifications simultaneously. 14. ? v cross is defined as the total variation of all crossing voltages of rising refclk and falling refclk#. this is the maximum allowed variance in v cross for any particular system. 15. refer to section 4.3.2.1 in the pci express base specification for information regarding ppm considerations.
intel ? 81341 and 81342 i/o processors december 2007 datasheet order number: 315039-003US 73 electrical specificationsintel ? 81341 and 81342 table 22. ddr2 output clock timings symbol parameter ddr2-400 ddr2-533 units notes min. max min. max t c2 ddr2 sdram clock cycle time average 5.00 3.75 ns t ch2 ddr2 sdram clock high time 2.25 1.69 ns t cl2 ddr2 sdram clock lowtime 2.25 1.69 ns t cs2 ddr2 sdram clock period jitter 100 -100 100 -100 ps t skew2 ddr2 sdram clock skew for any differential clock pair to any other clock pair 250 250 ps t skew3 ddr2 sdram clock skew for any clock pair to any system memory strobe 250 250 ps
intel ? 81341 and 81342electrical specifications intel ? 81341 and 81342 i/o processors datasheet december 2007 74 order number: 315039-003US 4.3.2 ddr2 sdram interface signal timings table 23. ddr2 sdram signal timings symbol parameter min. max units notes tvb1 dq, cb and dm write output valid time before dqs 0.530 ns 1, 3 tva1 dq, cb and dm write output valid time after dqs 0.530 ns 1, 3 tvb2 dqs write output valid time before m_ck (dqs early) 0.200 ns 1, 3 tva2 dqs write output valid time after m_ck (dqs late) 0.530 ns 1, 3 tv b 3 ma, ba, ras# , cas# , we# write output valid before m_ck rising edge. 4.900 ns 1, 3 tv a 3 ma, ba, ras# , cas# , we# write output valid after m_ck rising edge. 1.530 ns 1, 3 tv b 4 cs#, cke, odt write output valid before m_ck rising edge. unbuffered mode 2.090 ns 1, 3 tv a 4 cs#, cke, odt write output valid after m_ck rising edge. unbuffered mode 0.590 ns 1, 3 tv b 5 cs#, cke, odt write output valid before m_ck rising edge. registered mode 1.150 ns 1, 3 tv a 5 cs#, cke, odt write output valid after m_ck rising edge. registered mode 1.530 ns 1, 3 tis6 dq, cb read input setup time before dqs rising or falling edges. -0.670 ns 2 tih6 dq, cb read input hold time after dqs rising or falling edges. 1.250 ns 2 to v 7 m_ck[2:0] output valid from p_clkin or refclk 0.460 1.930 ns notes: 1. see figure 14, ddr2 sdram write timings on page 84 . 2. see figure 15, dqs falling edge output access time to/from m_ck rising edge on page 84 . timings valid when the dqs delay is programmed for the default 90 degree phase shift. 3. see figure 18, ac test load for ddr2 sdram signals on page 85 .
intel ? 81341 and 81342 i/o processors december 2007 datasheet order number: 315039-003US 75 electrical specificationsintel ? 81341 and 81342 4.3.3 peripheral bus interface signal timings table 24. peripheral bus interface signal timings symbol parameter min. nom. max. units a2d address to data wait-states 4 - 20 clks d2d data to data wait-states 4 - 20 clks rec recovery wait-states 1 - 20 clks n number of data phases 1 - 4 phases tasc address setup to ce# 25 30 - ns taso address setup to oe# 10 15 - ns tasw address setup to we# 25 30 - ns tah address hold from ce#,oe# nom - 5 rec 15 - ns tahw address hold from we# nom - 5 (rec+1) 15 - ns twce ce# pulse width nom - 5 (a2d + 2 + ((n - 1)(d2d + 2))) 15 -ns twoe oe# pulse width nom - 5 (a2d + 3 + ((n - 1)(d2d + 2))) 15 -ns twwe we# pulse width nom - 5 (a2d + 1) 15 - ns tdsw write data setup to we# nom - 5 (a2d + 1) 15 - ns tdhw write data hold from we# 10 15 20 ns tad1 1st read data access time from address - (a2d + 4) 15 nom - 11 ns tadn nth read data access time from address - (d2d + 2) 15 nom - 11 ns tcd read data access time from ce# - (a2d + 2) 15 nom - 11 ns toe read data access time from oe# 0 (a2d + 3) 15 nom - 11 ns tdh read data hold time from address, ce#, oe# 0 (rec + 2) 15 nom - 5 ns notes: 1. see figure 25, pbi output timings on page 88 and figure 26, pbi external device timings (flash) on page 89 .
intel ? 81341 and 81342electrical specifications intel ? 81341 and 81342 i/o processors datasheet december 2007 76 order number: 315039-003US 4.3.4 i 2 c/smbus interface signal timings table 25. i 2 c/smbus signal timings symbol parameter std. mode fast mode units note s min. max min. max fscl scl clock frequency 0 100 0 400 khz t buf bus free time between stop and start condition 4.7 1.3 s(1) t hdsta hold time (repeated) start condition 4 0.6 s (1,3) t low scl clock low time 4.7 1.3 s (1,2) thigh scl clock high time 4 0.6 s (1,2) tsusta setup time for a repeated start condition 4.7 0.6 s(1) thddat data hold time 0 3.45 0 0.9 s(1) tsudat data setup time 250 100 ns (1) t sr scl and sda rise time 1000 20 + 0.1c b 300 ns (1,4) t sf scl and sda fall time 300 20 + 0.1c b 300 ns (1,4) t susto setup time for stop condition 4 0.6 s(1) notes: 1. see figure 13, i2c interface signal timings on page 83 . 2. not tested. 3. after this period, the first clock pulse is generated. 4. c b = the total capacitance of one bus line, in pf. 5. std mode i 2 c signal timings apply for smbus timing.
intel ? 81341 and 81342 i/o processors december 2007 datasheet order number: 315039-003US 77 electrical specificationsintel ? 81341 and 81342 4.3.5 pci bus interface signal timings table 26. pci signal timings symbol parameter pci-x 133 pci-x 100 pci-x 66 pci 66 pci 33 units notes min. max min. max min. max min. max t ov1 clock to output valid delay 0.7 3.7 0.7 3.7 1 6 2 11 ns 1, 3 t of clock to output float delay 7 7 14 28 ns 1, 4 t is1 input setup to clock 1.2 1.7 3 7 ns 2 t ih1 input hold time from clock 0.5 0.5 0 0 ns 2 t rst reset active time 1 1 1 1 ms t rf reset active to output float delay 40 40 40 40 ns t is3 req64# to reset setup time 10 10 10 10 clocks t ih2 reset to req64# hold time 050050050050 ns t is4 pci-x initialization pattern to reset setup time 10 10 clocks t ih3 reset to pci-x initialization pattern hold time 050050 ns notes: 1. see the timing measurement conditions in; figure 11, output timing measurement waveforms on page 82 . 2. see the timing measurement conditions in: figure 12, input timing measurement waveforms on page 83 . 3. see figure 19, pci/pci-x tov(max) rising edge ac test load on page 86 , figure 20, pci/pci-x tov(max) falling edge ac test load on page 86 , figure 21, pci/pci-x tov(min) ac test load on page 86 . 4. for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification.
intel ? 81341 and 81342electrical specifications intel ? 81341 and 81342 i/o processors datasheet december 2007 78 order number: 315039-003US 4.3.6 pci express* differential transmitter (tx) output specifications table 27. pci express* rx input specifications symbol parameter min. nom max units notes v diffp-p differential input voltage 0.175 1.200 v 1 j total total output jitter 0.65 ui 2 v cm-ac ac common mode 100 mv 3 t reye receiver eye opening 0.35 ui 4 rl-diff rx differential return loss 12 db 5 rl-cm tx common mode return loss 6 db 5 z rx-out-dc dc differential output impedance 90 100 110 ohm 6 z rx-match-dc d+/d- impedance matching -5 +5 % 7 v rx-squelch squelch detect threshold 75 175 mv 8 cin rx ac coupled 75 nf 9 l skew-rx lane to lane skew at rx 20 ui 10 notes: 1. peak-peak differential voltage. v diffp-p = 2 v rmax. measured at the package pins of the receiver. see figure 12 . 2. max jitter tolerated by rx. this is the nominal value tolerated at the package pin of the receiver device. a receiver must therefore tolerate any additional jitter generated by the package to the die. 3. peak common mode value. |v d+ + v d- |/2 - v cm-dc(avg) 4. see figure 24, receiver eye opening (differential) on page 87 . 5. 50 mhz to 1.6 ghz. the driver output impedance shall result in a differential return loss greater than or equal to 15 db and a common mode return loss greater than or equal to 6 db over a frequency range of 50 mhz to 1.8 ghz. this output impedance requirement applies to all valid output levels. the reference impedance for return loss measurements is 100 ? for differential return loss and 25 ? for common mode (i.e. as measured by a vector network analyzer with 100 ? differential probes). note this is based on a nominal pci express* interconnect differential characteristic impedance of 100 ? . applicable during active (l0) and align states only. 6. dc differential mode impedance 100 ? 10% tolerance. 7. dc impedance matching between two lanes of a port. 8. peak-to-peak value. measured at the pin of the receiver. differential signal below this level will indicate a squelch condition. 9. all receivers shall be ac coupled to the media. 10. lane skew at the receiver that must be tolerated.
intel ? 81341 and 81342 i/o processors december 2007 datasheet order number: 315039-003US 79 electrical specificationsintel ? 81341 and 81342 table 28. pci express* tx output specifications symbol parameter min. nom max units notes ui unit interval 400 ps 1 v diffp-p differential output voltage 0.800 1.200 v 2 t rise , t fall driver rise/fall time 0.2 0.4 ui 3 v tx-cm-ac ac common mode 20 mv 4 v tx-cm-dc delta common mode active to sleep mode delta -50 +50 mv rl-diff tx differential return loss 15 db 5 rl-cm tx common mode return loss 6 db 5 z tx-out-dc dc differential output impedance 90 100 110 ? 6 z tx-match-dc d+/d- impedance matching -5 +5 % 7 l skew-tx lane to lane skew at tx 500 ps 8 j total total output jitter. 0.35 ui 9 t deye minimum transmitter eye opening. 0.65 ui 10 i tx-short short circuit current -100 100 ma 11 v tx-idle sleep mode voltage output 0 0 20 mv 12 notes: 1. 300 ppm. ui does not account for ssc dictated variations. no test load is necessarily associated with this value. this ui spec is a before transmission specification and represents the nominal time of each bit transmission or width. 2. peak-peak differential voltage. v diffp-p = 2 v dmax. specified at the package pins into a 100 ? test load as shown in figure 22, transmitter test load (100 w diff load) on page 86 . max level set by maximum single ended voltage after a reflection from an open. this value is for the first bit after a transition on the data lines. subsequent bits of the same polarity shall have an amplitude of 6 db (0.5 db) less as measured differentially peak to peak than the specified value. 3. 20C80% at transmitter. slower rise/fall times are better. 4. peak common mode value. |v d+ + v d- |/2 - v cm-dc(avg) 5. 50 mhz to 1.6 ghz. the driver output impedance shall result in a differential return loss greater than or equal to 15 db and a common mode return loss greater than or equal to 6 db over a frequency range of 50 mhz to 1.8 ghz. this output impedance requirement applies to all valid output levels. the reference impedance for return loss measurements is 100 ? for differential return loss and 25 ? for common mode (i.e. as measured by a vector network analyzer with 100 ? differential probes). note this is based on a nominal pci express* interconnect differential characteristic impedance of 100 ? . applicable during active (l0) and align states only. 6. dc differential mode impedance 100 ? 10% tolerance. all devices shall employ on-chip adaptive impedance matching circuits to ensure the best possible termination/zout for its transmitters (as well as receivers). 7. dc impedance matching between two lanes of a port. 8. between any two lanes within a single transmitter. 9. clock source ppm mismatch is in addition to this value. measured over 250 ui. 10. see figure 23, transmitter eye diagram on page 87 . 11. between any voltage from max supply to gnd with power on or off. 12. squelch condition. both signals brought to v cm-dc-|vd+ - vd-|
intel ? 81341 and 81342electrical specifications intel ? 81341 and 81342 i/o processors datasheet december 2007 80 order number: 315039-003US 4.3.7 pci express* differential receiver (rx) input specifications table 29. pci express* rx input specifications symbol parameter min. nom max units notes v diffp-p differential input voltage 0.175 1.200 v 1 j total total output jitter. 0.65 ui 2 v cm-ac ac common mode 100 mv 3 t reye receiver eye opening. 0.35 ui 4 rl-diff rx differential return loss 15 db 5 rl-cm tx common mode return loss 6 db 5 z rx-out-dc dc differential output impedance 90 100 110 ? 6 z rx-match-dc d+/d- impedance matching 0-5 +5 % 7 v rx-squelch squelch detect threshold 75 175 mv 8 cin rx ac coupled 400 pf 9 l skew-rx lane to lane skew at rx 20 ui 10 notes: 1. peak-peak differential voltage. v diffp-p = 2 * v rmax. measured at the package pins of the receiver. see figure 12 . 2. max jitter tolerated by rx. this is the nominal value tolerated at the package pin of the receiver device. a receiver must therefore tolerate any additional jitter generated by the package to the die. 3. peak common mode value. |v d+ + v d- |/2 - v cm-dc(avg) 4. see figure 24, receiver eye opening (differential) on page 87 . 5. 50 mhz to 1.6 ghz. the driver output impedance shall result in a differential return loss greater than or equal to 15 db and a common mode return loss greater than or equal to 6 db over a frequency range of 50 mhz to 1.8 ghz. this output impedance requirement applies to all valid output levels. the reference impedance for return loss measurements is 100 ? for differential return loss and 25 ? for common mode (i.e. as measured by a vector network analyzer with 100 ? differential probes). note this is based on a nominal pci express* interconnect differential characteristic impedance of 100 ? . applicable during active (l0) and align states only. 6. dc differential mode impedance 100 ? 10% tolerance. 7. dc impedance matching between two lanes of a port. 8. peak to peak value. measured at the pin of the receiver. differential signal below this level w ill indicate a squelch condition. 9. all receivers shall be ac coupled to the media. 10. lane skew at the receiver that must be tolerated.
intel ? 81341 and 81342 i/o processors december 2007 datasheet order number: 315039-003US 81 electrical specificationsintel ? 81341 and 81342 4.3.8 boundary scan test signal timings table 30. boundary scan test signal timings symbol parameter min. max units notes t jtf tck frequency 0 66 mhz t jtch tck high time 7.0 ns measured at 1.5 v (1) tjtcl tck low time 7.0 ns measured at 1.5 v (1) t jtcr tck rise time 5 ns 0.8 v to 2.0 v (1) t jtcf tck fall time 5 ns 2.0 v to 0.8 v (1) t jtis1 input setup to tck tdi , tms 3.0 ns (3) t jtih1 input hold from tck tdi , tms 2.0 ns (3) t jtov1 tdo output valid delay 4.25 13.25 ns relative to falling edge of tck (2) t of1 tdo float delay 4.25 13.25 ns relative to falling edge of tck (4) notes: 1. not tested. 2. see figure 11, output timing measurement waveforms on page 82 . 3. see figure 12, input timing measurement waveforms on page 83 . 4. a float condition occurs when the output current becomes less than i lo . float delay is not tested. see figure 11, output timing measurement waveforms on page 82 .
intel ? 81341 and 81342electrical specifications intel ? 81341 and 81342 i/o processors datasheet december 2007 82 order number: 315039-003US 4.4 ac timing waveforms figure 10. clock timing measurement waveforms figure 11. output timing measurement waveforms tch tcl tc vtch vih(min) vil(max) vtest vtcl vtest clk output float vtrise output delay rise output delay fall vtfall tov1 tov1 tof vtl vth
intel ? 81341 and 81342 i/o processors december 2007 datasheet order number: 315039-003US 83 electrical specificationsintel ? 81341 and 81342 figure 12. input timing measurement waveforms figure 13. i 2 c interface signal timings clk input val id v test v test v test t is1 t ih1 vtl vth vth vtl vmax sda scl t buf stop start t low t hdsta t high t sr t hddat t sf t sudat t susta repeated t hdsta t sp stop t susto start
intel ? 81341 and 81342electrical specifications intel ? 81341 and 81342 i/o processors datasheet december 2007 84 order number: 315039-003US figure 14. ddr2 sdram write timings figure 15. dqs falling edge output access time to/from m_ck rising edge m_ck dq s dq t va 1 t vb1 t vb 4/5 t va4/5 cs # t vb3 t va3 addr/cmd dqs# m_ck dqs max dqs min tvb2 tva2
intel ? 81341 and 81342 i/o processors december 2007 datasheet order number: 315039-003US 85 electrical specificationsintel ? 81341 and 81342 figure 16. ddr2 sdram read timings dqs d q t vb6 t va6 table 31. ac measurement conditions symbol pci-x pci ddr2 pbi units note s vth 0.6 v cc3p3 0.6 v cc3p3 m_vref +0.25 0 2.0 v v tl 0.25 v cc3p3 0.2 v cc3p3 m_vref -0.250 0.8 v v test 0.4 v cc3p3 0.4 v cc3p3 0.5 v cc1p8 1.5 v v trise 0.285 v cc3p3 0.285 v cc3p3 0.5 v cc1p8 1.5 v v tfall 0.615 v cc3p3 0.615 v cc3p3 0.5 v cc1p8 1.5 v v max 0.35 v cc3p3 0.4 v cc3p3 1.0 1.2 v slew rate 1.5 1.5 1.0 1.0 v/ns 1 notes: 1. input signal slew rate is measured between v il and v ih figure 17. ac test load for all signals except pci, pci-express and ddr2 figure 18. ac test load for ddr2 sdram signals output 50 pf tes t poin t 25 ? v tt output te s t point
intel ? 81341 and 81342electrical specifications intel ? 81341 and 81342 i/o processors datasheet december 2007 86 order number: 315039-003US figure 19. pci/pci-x t ov(max) rising edge ac test load figure 20. pci/pci-x t ov(max) falling edge ac test load figure 21. pci/pci-x t ov(min) ac test load figure 22. transmitter test load (100 ? diff load) output te st poin t 10 pf 25 ? output 10 pf 25 ? v cc33 tes t poin t output te s t point 10 pf 1k ? 1k ? v cc33 d+ d- + - v cm-dc 50 ? 50 ?
intel ? 81341 and 81342 i/o processors december 2007 datasheet order number: 315039-003US 87 electrical specificationsintel ? 81341 and 81342 figure 23. transmitter eye diagram figure 24. receiver eye opening (differential) note: transmitter vdiffp-p = 2 * vdmax ui vdmax vdmin tdeye note: transmitter vdiffp-p = 2 * vrmax ui vrmax vrmin treye
intel ? 81341 and 81342electrical specifications intel ? 81341 and 81342 i/o processors datasheet december 2007 88 order number: 315039-003US figure 25. pbi output timings pbi_clk a ce# oe# data(rd) address aawn...woddwm...woddrn...ro address++ dd a2d w/s d2d w/s recovery w/s read pbi_clk a ce# address a a wn ... wo d d rn ... ro we# data(wr) a2d w/s recovery w/s write tasc taso twoe twce tah twwe tdsw tdhw tasw tahw pbi output timings - read pbi output timings - write notes: (1) pbi_clk is provided as a virtual clock and is not available as an external signal. (2) timings are based on 66 mhz pbi_clk.
intel ? 81341 and 81342 i/o processors december 2007 datasheet order number: 315039-003US 89 electrical specificationsintel ? 81341 and 81342 figure 26. pbi external device timings (flash) figure 27. intel ? 81341 and 81342 i/o processors 1.2v/1.8v power sequencing system requirements pbi_clk a ce# oe# data(rd) address aawn...woddwm...woddrn...ro address++ dd a2d w/s d2d w/s recovery w/s read tad1 tcd toe tdh tdh tadn pbi external device timings (flash) notes: (1) pbi_clk is provided as a virtual clock and is not available as an external signal. (2) timings are based on 66 mhz pbi_clk. signal/ball names c oncerned: vcc1p8s, vcc1p2as and vcc1p2ds 1.8v supply should never exceed the 1.2v supply (analog or digital) when vcc1p2 < nominal the 3.3v supplies and vccvio supplies don?t have any sequencing requirements. 0 1.2 1.8 1.8v safe 1.8v safe 1.8v unsafe 1.8v unsafe 0 1.2 1.8 1.8v safe 1.8v safe 1.8v unsafe 1.8v unsafe 1.8v safe 1.8v safe 1.8v unsafe 1.8v unsafe

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